Y. Nakajima

发表

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

Tadahiko Sugibayashi, H. Hatayama, Isao Naritake, 1999 .

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).