N. Nakamura

Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design

T. Fujimaki, K. Higashi, N. Nakamura, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Test of fast-digital beamline feedback control at the photon factory

N. Nakamura, T. Katsura, 1993, Proceedings of International Conference on Particle Accelerators.

Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

N. Nakamura, E. Soda, S. Kondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM

N. Nakamura, Hideki Shibata, Hideshi Miyajima, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

A plasma damage resistant ultra low-k hybrid dielectric structure for 45nm node copper dual-damascene interconnects

H. Shibata, N. Nakamura, N. Matsunaga, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

H. Shibata, H. Kamijo, N. Nakamura, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

BEOL process integration technology for 45 nm node porous low-k/copper interconnects

H. Shibata, N. Nakamura, N. Matsunaga, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

Low resistance dual damascene process by new Al reflow using Nb liner

N. Nakamura, Minakshisundaran Balasubramanian Anand, Tomio Katata, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).