F. Matsuoka

发表

Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design

T. Fujimaki, K. Higashi, N. Nakamura, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Yield prediction techniques based on DFM rules and criticality for 65nm technology and beyond

F. Matsuoka, H. Murakami, T. Kojima, 2007, 2007 International Symposium on Semiconductor Manufacturing.

Quick-turnaround-time improvement for product development and transfer to mass production

F. Matsuoka, Nobuo Hayasaka, Hidetoshi Koike, 1998 .

Future perspective and scaling down roadmap for RF CMOS

T. Ohguro, H. Kimijima, E. Morifuji, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

The Fusion Experimental Reactor (FER)-design concepts

Hiroshi Yoshida, Kiyoshi Yoshida, Hiroshi Tsuji, 1989, IEEE Thirteenth Symposium on Fusion Engineering.

A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

H. Kimijima, E. Morifuji, F. Matsuoka, 2008, 2008 IEEE International Electron Devices Meeting.

Future perspective and scaling down roadmap for RF CMOS

T. Ohguro, H. Kimijima, E. Morifuji, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

T. Nakayama, F. Matsuoka, K. Maeguchi, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

T. Ohsawa, T. Higashi, F. Matsuoka, 2008, 2008 IEEE International SOI Conference.

Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

H. Naruse, E. Morifuji, F. Matsuoka, 2007, 2007 IEEE Symposium on VLSI Technology.

Combination of TCAD and physical MOSFET model for LSI development time reduction

Kohji Hashimoto, F. Matsuoka, Kazunari Ishimaru, 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

A 400 MHz 4.5 Mb synchronous BiCMOS SRAM with alternating bit-line loads

F. Matsuoka, A. Kawasumi, M. Kakumu, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

T. Yoshitomi, F. Matsuoka, M. Kakumu, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

J. Bonnouvrier, R. Augur, F. Arnaud, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array

F. Matsuoka, M. Noda, M. Takahashi, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

Scaling scenario of multi-level interconnects for future CMOS LSI

F. Matsuoka, Y. Asahi, H. Yoshimura, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Energy Saving Refrigeration System for Supermarket

F. Matsuoka, F. Unezaki, Y. Anzai, 2005, 2005 4th International Symposium on Environmentally Conscious Design and Inverse Manufacturing.

High performance bulk planar 20nm CMOS technology for low power mobile applications

O. Menut, Y. Liu, S. Samavedam, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell

F. Matsuoka, F. Masuoka, 2003 .

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

T. Noguchi, F. Matsuoka, T. Sanuki, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A 65nm low power CMOS platform with 0.495/spl mu/m/sup 2/ SRAM for digital processing and mobile applications

E. Morifuji, F. Matsuoka, S. Yamada, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

T. Noguchi, F. Matsuoka, H. Yoshimura, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation

S. Fujita, F. Matsuoka, T. Sanuki, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

T. Noguchi, F. Matsuoka, T. Sanuki, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

E. Morifuji, F. Matsuoka, S. Matsuda, 2006, IEEE Transactions on Electron Devices.