F. Lazzarino

Characterization of 8-in. wafers printed by nanoimprint lithography

C. Perret, Cécile Gourgon, R. Pelzer, 2004 .

Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

Olivier Joubert, C. Perret, Cécile Gourgon, 2005 .

A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node

L. Goux, N. Jossart, M. Jurczak, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Influence of pattern density in nanoimprint lithography

Olivier Joubert, C. Perret, Cécile Gourgon, 2003 .

Mold deformation in nanoimprint lithography

Patrick Schiavone, C. Perret, Cécile Gourgon, 2004 .

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).