Y. Morita

A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

J. Miyakoshi, M. Yoshimoto, H. Kawaguchi, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2007, 2007 IEEE Symposium on VLSI Circuits.