D. E. Ioannou

LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

S. Mitra, A. Salman, D. P. Ioannou, 2002, 2002 IEEE International SOI Conference.

Low voltage/low power sub 50 nm double gate SOI ratioed logic

S. Mitra, A. Salman, D. P. Ioannou, 2003, 2003 IEEE International Conference on SOI.