Mahmut E. Sinangil

发表

Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard

Anantha Chandrakasan, Minhua Zhou, Vivienne Sze, 2013, IEEE Journal of Selected Topics in Signal Processing.

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs

Benton H. Calhoun, Arijit Banerjee, Mahmut E. Sinangil, 2014, Fifteenth International Symposium on Quality Electronic Design.

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Anantha Chandrakasan, Mahmut E. Sinangil, A. Chandrakasan, 2013, IEEE Journal of Solid-State Circuits.

Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard

Anantha Chandrakasan, Minhua Zhou, Vivienne Sze, 2012, 2012 19th IEEE International Conference on Image Processing.

A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V

Anantha Chandrakasan, Mahmut E. Sinangil, Hugh Mair, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 28nm 0.6V low-power DSP for mobile applications

Anantha Chandrakasan, Uming Ko, Nathan Ickes, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

William J. Dally, Stephen G. Tell, Mahmut E. Sinangil, 2016, IEEE Journal of Solid-State Circuits.

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

David Blaauw, Dennis Sylvester, Yu-Der Chih, 2019, IEEE Journal of Solid-State Circuits.

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Anantha Chandrakasan, Minhua Zhou, Vivienne Sze, 2012, 2012 19th IEEE International Conference on Image Processing.

An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access

Anantha Chandrakasan, Mahmut E. Sinangil, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Uming Ko, Nathan Ickes, Jie Gu, 2012, IEEE Journal of Solid-State Circuits.

A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

Mahmut E. Sinangil, Hung-Jen Liao, Yen-Ting Lin, 2019, IEEE Journal of Solid-State Circuits.

A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

Anantha Chandrakasan, Vivienne Sze, Mahmut E. Sinangil, 2009, IEEE Journal of Solid-State Circuits.

Challenges and Directions for Low-Voltage SRAM

Anantha Chandrakasan, Mahmut E. Sinangil, Masood Qazi, 2011, IEEE Design & Test of Computers.

Low-power and application-specific SRAM design for energy-efficient motion estimation

Mahmut E. Sinangil, 2012 .

Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics

Anantha P. Chandrakasan, Mahmut E. Sinangil, Andreas J. Gotterba, 2017, IEEE Journal of Solid-State Circuits.

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Anantha Chandrakasan, Mahmut E. Sinangil, Masood Qazi, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Technologies for Ultradynamic Voltage Scaling Circuits such as logic cells, static random access memories, analog-digital converters and dc-dc converters can be used as building blocks for applications that can function efficiently over a wide range of supply voltages.

Anantha P. Chandrakasan, Denis C. Daly, Vivienne Sze, 2010 .

Technologies for Ultradynamic Voltage Scaling

Naveen Verma, Denis C. Daly, Anantha Chandrakasan, 2010, Proceedings of the IEEE.

Self-aware computing in the Angstrom processor

George Kurian, Srinivas Devadas, Anantha Chandrakasan, 2012, DAC Design Automation Conference 2012.

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

Nathan Ickes, Srinivas Devadas, Anantha Chandrakasan, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Anantha P. Chandrakasan, Naveen Verma, Mahmut E. Sinangil, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology

Yen-Ting Lin, Jonathan Chang, Mahmut E. Sinangil, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

Mahmut E. Sinangil, Rawan Naous, Yih Wang, 2021, IEEE Journal of Solid-State Circuits.

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).