Amit Sanghani

Test method and scheme for low-power validation in modern SOC integrated circuits

Amit Laknaur, Bonita Bhaskaran, Amit Sanghani, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Bo Yang, Chunsheng Liu, Amit Sanghani, 2011, 2011 Design, Automation & Test in Europe.

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

Bo Yang, Chunsheng Liu, Amit Sanghani, 2011, 29th VLSI Test Symposium.

A programmable method for low-power scan shift in SoC integrated circuits

Krishnendu Chakrabarty, Bonita Bhaskaran, Amit Sanghani, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Dynamic docking architecture for concurrent testing and peak power reduction

Amit Sanghani, Anubhav Sinha, Shantanu Sarangi, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Flexible scan interface architecture for complex SoCs

Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).