S. Sakiyama

Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application

T. Morie, A. Matsumoto, S. Sakiyama, 2007, 2007 IEEE Symposium on VLSI Circuits.

A selfconfigurable digital neuro chip addressing to multi-network architecture

T. Kouda, S. Sakiyama, S. Maruno, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

Mixed body-bias techniques with fixed Vt and Ids generation circuits

Y. Ikeda, S. Sakiyama, M. Sumita, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

A 200 MIPS image signal multiprocessor on a single chip

S. Sakiyama, M. Maruyama, H. Nakahira, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

High efficiency and latch-up free switched capacitor up converter on FD-SOI technology

A. Matsuzawa, S. Sakiyama, M. Kinoshita, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

S. Sakiyama, Y. Tokunaga, S. Dosho, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique

A. Matsuzawa, S. Sakiyama, J. Kajiwara, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution

T. Morie, S. Sakiyama, Y. Tokunaga, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

Y. Ikeda, S. Sakiyama, M. Sumita, 2004, IEEE Journal of Solid-State Circuits.

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

T. Morie, A. Matsumoto, S. Sakiyama, 2008, IEEE Journal of Solid-State Circuits.