D. Plass

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

W. Huott, R. Houle, R. Joshi, 2007, 2007 IEEE Symposium on VLSI Circuits.

Storage hierarchy to support a 600 MHz G5 S/390 microprocessor

C. Ford, M. Blake, D. Plass, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities

R. Kanj, W. Huott, R. Houle, 2008, 2008 IEEE Symposium on VLSI Circuits.