J. P. Anita

发表

Design of a low power, high speed double tail comparator

S. Aakash, A. Anisha, G. Jaswanth Das, 2017, 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT).

Multiple fault diagnosis with improved diagnosis resolution for VLSI circuits

J. P. Anita, P. T Vaathi, 2010, 2010 Second International conference on Computing, Communication and Networking Technologies.

Efficient don't-care filling method to achieve reduction in test power

J. P. Anita, V. Sinduja, Siddharth Raghav, 2015, 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Lateral prediction in adaptive cruise control using adaptive particle filter

J. P. Anita, P. Sudheesh, Jattin Badrinath, 2017, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

J. P. Anita, Anju Asokan, 2016 .

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

J. P. Anita, Navya Mohan, 2016, Int. J. Math. Model. Numer. Optimisation.

Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power

Ashwin Swaminathan, J. P. Anita, T. S. Gokkul Nath, 2016, SSCC.

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

J. P. Anita, P. Sudheesh, 2016, Int. J. High Perform. Syst. Archit..

AXI based DMA Memory System Testbench Architecture Using UVM Harness Technique

J. P. Anita, Anjali, 2019, 2019 9th International Conference on Advances in Computing and Communication (ICACC).

Novel Approach for Multiple Arbitrary Faults Diagnosis in Combinational Circuits

J. P. Anita, P. T. Vanathi, Reeja Raju, 2011, 2011 International Conference on Process Automation, Control and Computing.

Nonlinear state estimation of wind turbine

J. P. Anita, P. Sudheesh, P. Sudev, 2017, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

J. P. Anita, Ch. Narasimha Kumar, A. Madhumitha, 2019, 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI).

Structured DFT Based Analysis of Standard Benchmark Circuits

J. P. Anita, H. Harshita Shravani, 2020 .

Pattern Generation and Test Compression Using PRESTO Generator

J. P. Anita, Annu Roy, 2017, SSCC.

Tracking of GPS Parameters Using Particle Filter

M. Nishanth, J. P. Anita, P. Sudheesh, 2017, SSCC.

A compaction based MT filling technique for low-power test set generation

J. P. Anita, G. Venu Madhavi, 2016, 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS).

Estimation and Tracking of a Ballistic Target Using Sequential Importance Sampling Method

J. P. Anita, P. Sudheesh, J. Ramnarayan, 2017, SSCC.

Modified carry select adder for power and area reduction

S. Aakash, T. Abhiram, J. P. Anita, 2017, 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT).

Particle Filtering Technique for Fast Fading Shadow Power Estimation in Wireless Communication

J. P. Anita, P. Sudheesh, S. Jaiyant Gopal, 2017, SIRS.

Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD

J. P. Anita, Antony Thomas, 2019, 2019 International Conference on Communication and Electronics Systems (ICCES).

Test volume reduction for logic circuits by sharing of test patterns

J. P. Anita, K. A. Radhika, 2018 .

Improving diagnostic test coverage from detection test set for logic circuits

J. P. Anita, Bommidi Madhan, 2019 .

Multiple Fault Diagnosis and Test Power Reduction Using Genetic Algorithms

J. P. Anita, P. T. Vanathi, 2012 .

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

J. P. Anita, P. T. Vanathi, 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults

J. P. Anita, N. Mohan, 2021, Integr..

Z-Set and Independent Fault Set based Fault Pair Collapsing for Fault List Reduction

J. P. Anita, J. P Anita, 2014 .