T.A. Kwasniewski

A 10-Gb/s CMOS sample-and-hold phase detector using dual substrate technique

Z.W.Y. Hui, T.A. Kwasniewski, 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

High-speed Viterbi decoder for W-LAN and broadband applications

T.A. Kwasniewski, A.R. Abdul Shakoor, V. Szwarc, 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..

A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

T.A. Kwasniewski, M. Thamsirianunt, T. Kwasniewski, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Analog DLL-based period synthesis circuit

T.A. Kwasniewski, Z. Farhad, 2005, Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005..

A 40-GHz Frequency Divider in 90-nm CMOS Technology

T.A. Kwasniewski, M. Usama, 2006, 2006 IEEE North-East Workshop on Circuits and Systems.

A multiple-rotating-clock-phase architecture for digital data recovery circuits using Verilog-A

T.A. Kwasniewski, S.I. Ahmed, 2005, BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005..

Efficient simulation of jitter tolerance for all-digital data recovery circuits

T.A. Kwasniewski, S.I. Ahmed, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

Overview of oversampling clock and data recovery circuits

T.A. Kwasniewski, S.I. Ahmed, 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

Metastability analysis OF CMOS current mode logic latches

T.A. Kwasniewski, M. Usama, 2005, Canadian Conference on Electrical and Computer Engineering, 2005..