Tetsuo Yamasaki

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

Hiroaki Terada, Toshiyuki Tamura, O. Tomisawa, 1989 .

VLSI implementation of a variable-length pipeline scheme for data-driven processors

Hiroaki Terada, Toshiyuki Tamura, O. Tomisawa, 1989 .

A 40 MFLOPS 32-bit floating-point processor

Toshiyuki Tamura, O. Tomisawa, Hiroaki Nishikawa, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.