Shih-Hsu Huang

发表

Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions

Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai, 2002, Asia-Pacific Conference on Circuits and Systems.

Co-synthesis of data paths and clock control paths for minimum-period clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Live demonstration: A low-power high-level synthesis system

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Low-power timing closure methodology for ultra-low voltage designs

Shih-Hsu Huang, Wen-Pin Tu, Shih-Chieh Chang, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction

Shih-Hsu Huang, Yi-Chun Chang, Shih-Chieh Chang, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Operation Scheduling for False Loop Free Circuits

Shih-Hsu Huang, Chun-Hua Cheng, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Module binding for low power clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2008, IEICE Electron. Express.

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs

Shih-Hsu Huang, Hua-Hsin Yeh, Shih-Chieh Chang, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TSV-aware 3D test wrapper chain optimization

Shih-Hsu Huang, Yu-Yi Wu, Shih-Hsu Huang, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization

Shih-Hsu Huang, 2018, 2018 11th International Workshop on Network on Chip Architectures (NoCArc).

Simultaneous data path synthesis and clock skew scheduling for leakage and glitch power minimization

Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, 2014, 2014 International Symposium on Next-Generation Electronics (ISNE).

3D IC test scheduling with test pads considered

Shih-Hsu Huang, Chun-Hua Cheng, Ming-Hsuan Hsu, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Top-level activity-driven clock tree synthesis with clock skew variation considered

Shih-Hsu Huang, Wei-Kai Cheng, Te-Jui Wang, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Minimum-Period Register Binding

Shih-Hsu Huang, Chun-Hua Cheng, Shih-Hsu Huang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimizing peak current via opposite-phase clock tree

Shih-Hsu Huang, Yow-Tyng Nieh, Sheng-Yu Hsu, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Design Automation of Fuzzy Rules Based on Trapezoid-Shaped Membership Functions

Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai, 2004 .

VLSI implementation of type-2 fuzzy inference processor

Shih-Hsu Huang, Yi-Rung Chen, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A practical interconnect driven ASIC design procedure

Shih-Hsu Huang, Mely Chen Chi, J. M. Tseng, 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

Effective and efficient layer assignment for minimizing the temperature rise of large three-dimensional circuits

Shih-Hsu Huang, Hua-Hsin Yeh, 2012, 2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

An industrial design methodology for the synthesis of OCV-aware top-level clock tree

Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou, 2017, 2017 6th International Symposium on Next Generation Electronics (ISNE).

TSV number minimization using alternative paths

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hsien Kuo, 2011, 2011 IEEE International Conference on IC Design & Technology.

An Effective Approach for Building Low-Power General Activity-Driven Clock Trees

Shih-Hsu Huang, Wei-Kai Cheng, Chen-Hsien Lin, 2018, 2018 International SoC Design Conference (ISOCC).

A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design

Shih-Hsu Huang, En-Hui Zhang, 2020, 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan).

An Efficient Membership Function Representation for High-Resolution Fuzzy Systems

Shih-Hsu Huang, Jian-Yuan Lai, 2001 .

Overview of the 2017 CAD contest at ICCAD: Invited paper

Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake, 2017, ICCAD.

Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew

Shih-Hsu Huang, Wen-Pin Tu, Tsung-Tang Lin, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Ting Yen, 2007, EUC Workshops.

Operation scheduling for the synthesis of false loop free circuits

Shih-Hsu Huang, Chun-Hua Cheng, 2007, IEICE Electron. Express.

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Softsign Function Hardware Implementation Using Piecewise Linear Approximation

Shih-Hsu Huang, Chih-Hsiang Chang, En-Hui Zhang, 2019, 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

A high-speed VLSI fuzzy logic controller with pipeline architecture

Shih-Hsu Huang, Jian-Yuan Lai, Shih-Hsu Huang, 2001, 10th IEEE International Conference on Fuzzy Systems. (Cat. No.01CH37297).

New activity-driven clock tree design methodology for low power clock gating

Shih-Hsu Huang, Chen-Hsien Lin, Jia-Hong Jian, 2017, 2017 6th International Symposium on Next Generation Electronics (ISNE).

3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints

Shih-Hsu Huang, Yen-Chun Ko, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Accurate TSV Number Minimization in High-Level Synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hung Lee, 2011, J. Inf. Sci. Eng..

Synthesis of nonzero clock skew circuits

Shih-Hsu Huang, Yow-Tyng Nieh, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of false loop free circuits

Yen-Jen Oyang, Shih-Hsu Huang, Ta-Yung Liu, 1995, ASP-DAC '95.

Surge current minimization in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Jheng-Fu Yeh, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Clock Period Minimization of Non-Zero Clock Skew Circuits

Shih-Hsu Huang, Yow-Tyng Nieh, 2003, ICCAD 2003.

Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power

Shih-Hsu Huang, Hsu-Yu Kao, Chu-Han Hsu, 2019, 2019 2nd International Conference on Communication Engineering and Technology (ICCET).

An ILP Approach to the Slack Driven Scheduling Problem

Shih-Hsu Huang, Chun-Hua Cheng, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A new approach to schedule operations across nested-ifs and nested-loops

Yen-Jen Oyang, Shih-Hsu Huang, Yu-Chin Hsu, 1992, MICRO 1992.

A formal approach to the slack driven scheduling problem in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Timing driven power gating in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design

Shih-Hsu Huang, Chun-Lung Hsu, Shi-Rou Lin, 2020, 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan).

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits

Yen-Jen Oyang, Shih-Hsu Huang, Yu-Chin Hsu, 1995, Microprocess. Microprogramming.

Teaching three-dimensional system-in-package design automation in a semester course

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2011, 2011 IEEE International Conference on Microelectronic Systems Education.

Overview of the 2017 CAD contest at ICCAD: Invited paper

Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011

Shih-Hsu Huang, Younghyun Kim, Wen-Pin Tu, 2011, MSE.

Synthesis of Anti-Aging Gated Clock Designs

Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan, 2009, J. Inf. Sci. Eng..

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management

Shih-Hsu Huang, Chun-Hua Cheng, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

State re-encoding for peak current minimization

Shih-Hsu Huang, Yow-Tyng Nieh, Chia-Ming Chang, 2006, ICCAD.

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2006 .

A Mechanism for Adjustable-Delay-Buffer Selection to Dynamically Control Clock Skew

Shih-Hsu Huang, Chia-Wen Chang, 2018, 2018 International Conference on System Science and Engineering (ICSSE).

A high speed fuzzy inference processor with dynamic analysis and scheduling capabilities

Shih-Hsu Huang, Jian-Yuan Lai, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Watermark-strength-aware register binding

Shih-Hsu Huang, Chun-Hua Cheng, Tsung-Tang Lin, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Hardware Implementation for Multiple Activation Functions

Shih-Hsu Huang, Chih-Hsiang Chang, Hsu-Yu Kao, 2019, 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).

A timing driven approach for crosstalk minimization in gridded channel routing

Shih-Hsu Huang, Yi-Siang Hsu, 2002, Asia-Pacific Conference on Circuits and Systems.

Fast multi-domain clock skew scheduling for peak current reduction

Shih-Hsu Huang, Yow-Tyng Nieh, Chia-Ming Chang, 2006, Asia and South Pacific Conference on Design Automation, 2006..

3D Test Wrapper Chain Optimization with I/O Cells Binding Considered

Shih-Hsu Huang, Jin-Fu Li, Hsu-Yu Kao, 2019, 2019 International 3D Systems Integration Conference (3DIC).

An effective floorplan-based power distribution network design methodology under reliability constraints

Shih-Hsu Huang, Chu-Liao Wang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Non-uniform clock mesh synthesis under temperature constraints

Shih-Hsu Huang, Shun-Cheng Yang, 2017, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).

A Timing Driven Crosstalk Optimizer for Gridded Channel Routing

Shih-Hsu Huang, Chiu-Cheng Lin, Yi-Siang Hsu, 2004, IEICE Trans. Inf. Syst..

3D IC design partitioning for temperature rise minimization

Shih-Hsu Huang, Hua-Hsin Yeh, Kuan-Hui Li, 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Low-Power Small-Area $3\times 3$ Convolution Hardware Design

Shih-Hsu Huang, Xin-Jia Chen, 2020, 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan).

A Practical Interconnect-Driven Design Methodology for Low Power ASIC Designs

Shih-Hsu Huang, Mely Chen Chi, Hsu-Ming Hsiao, 2001 .

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2010, J. Inf. Sci. Eng..

A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

Shih-Hsu Huang, Chun-Hua Cheng, Chih-Hung Lee, 2010, 2010 International Symposium on Computer, Communication, Control and Automation (3CA).

Opposite-Phase Clock Tree for Peak Current Reduction

Shih-Hsu Huang, Yow-Tyng Nieh, Sheng-Yu Hsu, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Effective Approach to Designing a Power Distribution Network at the Post-Floorplan Stage

Shih-Hsu Huang, Yow-Tyng Nieh, Chu-Liao Wang, 2004 .

An ILP approach to surge current minimization in high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Jheng-Fu Yeh, 2009, IEICE Electron. Express.

Peak Power Minimization through Power Management Scheduling

Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

TSV sharing through multiplexing for TSV count minimization in high-level synthesis

Shih-Hsu Huang, Wen-Pin Tu, Yen-Hsin Lee, 2011, 2011 IEEE International SOC Conference.

A formal approach to slack-driven high-level synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits

Shih-Hsu Huang, Hua-Hsin Yeh, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Clock skew scheduling with race conditions considered

Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Hsu Huang, 2007, TODE.

Utilizing Power Management and Timing Slack for Low Power in High-Level Synthesis

Shih-Hsu Huang, Chun-Hua Cheng, Zong-Han Xie, 2018, 2018 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization

Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng, 2009, J. Inf. Sci. Eng..

Clock Period Minimization with Minimum Delay Insertion

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2007, 2007 44th ACM/IEEE Design Automation Conference.

IC Camouflaging by Using Universal Gates under Timing Constraints

Shih-Hsu Huang, Po-Chieh Chang, 2019, 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).

Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction

Shih-Hsu Huang, Wei-Kai Cheng, Jian-Kai Chen, 2018, 2018 International SoC Design Conference (ISOCC).

High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions

Shih-Hsu Huang, Jian-Yuan Lai, Shih-Hsu Huang, 2005, J. Inf. Sci. Eng..

Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors

Shih-Hsu Huang, Che-Wei Tung, Che-Wei Tung, 2019, 2019 2nd International Conference on Communication Engineering and Technology (ICCET).

Clock Period Minimization with Minimum Leakage Power

Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh, 2015, ACM Trans. Design Autom. Electr. Syst..

Race-condition-aware retiming

Shih-Hsu Huang, Yow-Tyng Nieh, Wei-Chieh Yu, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Power-mode-aware buffer synthesis for low-power clock skew minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2016, IEICE Electron. Express.

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management

Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, 2006, JCIS.

NBTI-aware dual threshold voltage assignment for leakage power reduction

Shih-Hsu Huang, Wen-Pin Tu, Mely Chen Chi, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A new approach to schedule operations across nested-ifs and nested-loops

Yen-Jen Oyang, Shih-Hsu Huang, Yu-Chin Hsu, 1992, MICRO 25.

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol

Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

An EDA course module for the topic of reliability using automotive electronics as applications

Shih-Hsu Huang, Wen-Pin Tu, Mely Chen Chi, 2013, 2013 3rd Interdisciplinary Engineering Design Education Conference.

Temperature rise minimization through simultaneous layer assignment and thermal through-silicon-via planning

Shih-Hsu Huang, Hua-Hsin Yeh, Chen-Yu Huang, 2013, 2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

PVT-variations-tolerant clock design using self-correcting adjustable delay buffers

Shih-Hsu Huang, Wen-Pin Tu, Hsin-Heng Lu, 2014, 2014 International Symposium on Next-Generation Electronics (ISNE).

Three-dimension scheduling under multi-cycle interconnect communications

Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, 2005, IEICE Electron. Express.

Leakage-power-aware clock period minimization

Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2012, 17th Asia and South Pacific Design Automation Conference.

A reliable clock tree design methodology for ASIC designs

Shih-Hsu Huang, Mely Chen Chi, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

High-Level Synthesis for Minimum-Area Low-Power Clock Gating

Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li, 2012, J. Inf. Sci. Eng..

Power-Management Scheduling for Peak Power Minimization

Shih-Hsu Huang, Chun-Hua Cheng, 2008, J. Inf. Sci. Eng..

A Design Framework for Hardware Approximation of Deep Neural Networks

Shih-Hsu Huang, Hsu-Yu Kao, Wei-Hung Lin, 2019, 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Minimum buffer insertions for clock period minimization

Shih-Hsu Huang, Wei-Lun Huang, Guan-Yu Jhuo, 2010, 2010 International Symposium on Computer, Communication, Control and Automation (3CA).

A new approach to schedule operations across nested-ifs and nested-loops

Yen-Jen Oyang, Shih-Hsu Huang, Yu-Chin Hsu, 1995, MICRO 25.

Utilizing clock skew for timing reliability improvement

Shih-Hsu Huang, Man-Lin Huang, Yu-Hui Lin, 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

A Semester Course for Teaching Three-Dimensional System-in-Package Design Automation

Shih-Hsu Huang, Wen-Pin Tu, Chun-Hua Cheng, 2014 .

Performance and Power Driven Non-Zero Skew Clock Tree Design Methodology

Shih-Hsu Huang, Yow-Tyng Nieh, Yu-Hui Lin, 2004 .

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process

Shih-Hsu Huang, Che-Wei Tung, Che-Wei Tung, 2020, IEEE Access.

MINIMUM-POWER CLOCK GATING

Chia-Ming Chang, Shih-Hsu Huang, Chun-Hua Cheng, 2009 .

A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs

Shih-Hsu Huang, Man-Lin Huang, Chu-Liao Wang, 2007, EUC.

A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains

Shih-Hsu Huang, Yow-Tyng Nieh, Chia-Ming Chang, 2007, J. Inf. Sci. Eng..

Layer assignment for maximizing the reliability of 3D ICs

Shih-Hsu Huang, Chun-Hua Cheng, Chun-Wei Lee, 2016, 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Test wrapper bandwidth assignment for minimizing the SoC test application time

Shih-Hsu Huang, Chun-Hua Cheng, Cheng-Hsun Nien, 2015, 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Opposite-phase register switching for peak current minimization

Shih-Hsu Huang, Yow-Tyng Nieh, Chia-Ming Chang, 2009, TODE.

Downlink base transmit station modulator in WCDMA system

Shih-Hsu Huang, Kai-Hao Bai, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Implementing Optimal Clock Schedule with Minimum Cost

Shih-Hsu Huang, Shi-Zhi Liu, 2003 .

Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function

Shih-Hsu Huang, Wei-Hung Lin, Yu-Hsuan Wu, 2020, 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan).

Floorplanning with clock tree estimation

Shih-Hsu Huang, Tsai-Ming Hsieh, Chih-Yuan Lin, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A New Scheduling Algorithm for Automatic Synthesis of the Control Blocks of Multi-way Branch Architectures

Shih-Hsu Huang, 2000 .

StateRe-Encoding forPeakCurrent Minimization

Chia-Ming Chang, Shih-Hsu Huang, Yow-Tyng Nieh, 2006 .

An effective low powr design methodology based on interconnect prediction

Shih-Hsu Huang, 2001, SLIP '01.

Grouping and placement of memory BIST controllers for test application time minimization

Shih-Hsu Huang, Chun-Hua Cheng, Chang-Han Yeh, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Kai Cheng, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

A Gridded Channel Routing Approach for the Minimization of Crosstalk Delay Degradation

Shih-Hsu Huang, Yi-Siang Hsu, 2002 .

Temperature-dependent test scheduling with TAM bus wire assignment considered for core-based SoC designs

Shih-Hsu Huang, Ching-Chun Chiu, 2015, 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Race-condition-aware clock skew scheduling

Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Type-matching clock tree for zero skew clock gating

Shih-Hsu Huang, Yu-Sheng Lu, Chia-Ming Chang, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Clock Period Minimization of Non-Zero Clock Skew Circuits

Shih-Hsu Huang, Yow-Tyng Nieh, 2003, ICCAD.

Minimum Inserted Buffers for Clock Period Minimization

Shih-Hsu Huang, Wei-Lun Huang, Guan-Yu Jhuo, 2011, J. Inf. Sci. Eng..

On-chip-variation-aware power-mode-aware buffer synthesis for clock skew minimization

Shih-Hsu Huang, Yu Lee, 2017, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Wafer bonding type selection for 3D IC designs

Shih-Hsu Huang, Chun-Hua Cheng, Hua-Hsin Yeh, 2013, 2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Low-power anti-aging zero skew clock gating

Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, 2013, TODE.

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization

Shih-Hsu Huang, Chun-Hua Cheng, Wei-Shuo Tzeng, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A design partitioning algorithm for Three Dimensional Integrated Circuits

Shih-Hsu Huang, Mely Chen Chi, Hua-Sin Ye, 2010, 2010 International Symposium on Computer, Communication, Control and Automation (3CA).

Reliability-driven high-level synthesis with clock frequency considered

Shih-Hsu Huang, Chun-Hua Cheng, Wen-Zen Cheng, 2016, 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

High-Speed Fuzzy Inference Processor Using Active Rules Identification

Shih-Hsu Huang, Jian-Yuan Lai, Shi-Zhi Liu, 2006, JCIS.

2.5D system synthesis methodology under performance, power and thermal constraints

Shih-Hsu Huang, Shih-Chieh Chang, Chung-Han Chou, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Shih-Hsu Huang, Jin-Fu Li, Chun-Lung Hsu, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators

Shih-Hsu Huang, Hsu-Yu Kao, Wei-Hung Lin, 2021, 2021 18th International SoC Design Conference (ISOCC).

Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing

Shih-Hsu Huang, En-Hui Zhang, 2021, 2021 IEEE International Conference on Consumer Electronics (ICCE).

Block-Based Compression for Reducing Indexing Cost of DNN Accelerators

Shih-Hsu Huang, Hsu-Yu Kao, Yui-Kai Weng, 2021, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

ECO Timing Optimization with Data Paths and Clock Paths Considered

Shih-Hsu Huang, Jui-Hung Hung, Jia-Xiang Tang, 2021, 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Hardware Implementation for Fending off Side-Channel Attacks

Shih-Hsu Huang, Yui-Kai Weng, Yi-Liang Hong, 2021, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW).

Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations

Shih-Hsu Huang, Hsu-Yu Kao, Yui-Kai Weng, 2021, Sensors.

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing

Shih-Hsu Huang, Hsu-Yu Kao, Xin-Jia Chen, 2021, Sensors.

State Re-Encoding for Peak Current Minimization

Shih-Hsu Huang, Yow-Tyng Nieh, Chia-Ming Chang, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.