Yu-Tsun Chien

A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop

Chua-Chin Wang, Ying-Pei Chen, Yu-Tsun Chien, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A methodology for analog circuit macromodeling

Yu-Tsun Chien, L.T. Pileggi, R. Batra, 2004, Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004..

Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization

Xin Li, Brian Taylor, Yu-Tsun Chien, 2007, ICCAD 2007.

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

Chua-Chin Wang, Ying-Pei Chen, Yu-Tsun Chien, 2000, VLSI Design.

SPEED: synthesis of high-performance large scale analog/mixed signal circuit

Gin-Kou Ma, Li-Ren Huang, Yu-Tsun Chien, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Design of an inter-plane circuit for clocked PLAs

Chua-Chin Wang, Ying-Pei Chen, Yu-Tsun Chien, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network

Cheng-Fa Tsai, Chua-Chin Wang, Yu-Tsun Chien, 2001, J. Inf. Sci. Eng..

Design of an Inter-plane Circuit for Clocked PLAs

Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen, 2002, VLSI Design.