JaleelAamer

Maximizing Heterogeneous Processor Performance Under Power Constraints

EeckhoutLieven, EyermanStijn, AdilehAlmutaz, 2016 .

In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)

JacobBruce, JaleelAamer, 2006 .

Adaptive insertion policies for high performance caching

N PattYale, K QureshiMoinuddin, EmerJoel, 2007 .

High performance cache replacement using re-reference interval prediction (RRIP)

EmerJoel, JaleelAamer, C SteelySimon, 2010 .

Non-monopolizable caches

Abu-GhazalehNael, JaleelAamer, PonomarevDmitry, 2012 .

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures

LustigDaniel, FlemingKermin, AdlerMichael, 2015 .