Ilya Issenin

发表

Mitigating soft error failures for multimedia applications by selective data protection

Aviral Shrivastava, Nikil D. Dutt, Nalini Venkatasubramanian, 2006, CASES '06.

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures

Aviral Shrivastava, Yunheung Paek, Nikil D. Dutt, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multiprocessor system-on-chip data memory customization for embedded array-intensive applications

Nikil Dutt, Ilya Issenin, 2007 .

Compilation techniques for energy reduction in horizontally partitioned cache architectures

Aviral Shrivastava, Nikil D. Dutt, Ilya Issenin, 2005, CASES '05.

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies

Erik Brockmeyer, Nikil D. Dutt, Ilya Issenin, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications

Erik Brockmeyer, Nikil D. Dutt, Ilya Issenin, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Software controlled memory layout reorganization for irregular array access patterns

Yunheung Paek, Nikil D. Dutt, Ilya Issenin, 2007, CASES '07.

Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Nikil D. Dutt, Ilya Issenin, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures

Aviral Shrivastava, Nikil D. Dutt, Ilya Issenin, 2008, 2008 Asia and South Pacific Design Automation Conference.

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications

Yunheung Paek, Nikil D. Dutt, Sudeep Pasricha, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using FORAY Models to Enable MPSoC Memory Optimizations

Nikil D. Dutt, Ilya Issenin, 2007, International Journal of Parallel Programming.

Data Reuse Driven Memory and Network-On-Chip Co-Synthesis

Nikil D. Dutt, Ilya Issenin, 2007, IESS.

DRDU: A data reuse analysis technique for efficient scratch-pad memory management

Erik Brockmeyer, Nikil D. Dutt, Miguel Corbalan, 2007, TODE.

Compiler driven data layout optimization for regular/irregular array access patterns

Yunheung Paek, Nikil D. Dutt, Sudeep Pasricha, 2008, LCTES '08.

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications

Aviral Shrivastava, Nikil D. Dutt, Nalini Venkatasubramanian, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Profile-based dynamic voltage scheduling using program checkpoints

Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

FORAY-GEN: automatic generation of affine functions for memory optimizations

Nikil D. Dutt, Ilya Issenin, N. Dutt, 2005, Design, Automation and Test in Europe.

Data reuse analysis technique for software-controlled memory hierarchies

Erik Brockmeyer, Nikil D. Dutt, Miguel Corbalan, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Using FORAY models to enable MPSoC memory optimizations

Nikil Dutt, Ilya Issenin, 2008 .