P. Israsena

VLSI design of bit-retimed and pipelined recursive filters

P. Israsena, 2003, ASIC, 2003. Proceedings. 5th International Conference on.

Hardware Implementation of a TEA-Based Lightweight Encryption for RFID Security

P. Israsena, S. Wongnamkum, 2008 .

A TDMA/TDD processing unit IP core for WLL cell station targeting FPGA implementation

P. Duangtanoo, C. Meenakarn, P. Israsena, 2003, ASIC, 2003. Proceedings. 5th International Conference on.

Accurate power estimation technique with application to low-power recursive digital filter design

S. Summerfield, P. Israsena, 2001 .

Design andImplementation ofLowPowerHardware Encryption forLowCostSecure RFIDUsingTEA

P. Israsena, 2005 .

NOVEL PATTERN-BASED POWER ESTIMA' MODEL 'ION TOOL WITH ACCURATE GLITCH (NG

S. Summerfield, P. Israsena, 2000 .