R. T. Cakici

Gate leakage reduction for scaled devices using transistor stacking

Kaushik Roy, Amit Agarwal, Chris H. Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

SPICE simulations of data path timing margins after dielectric breakdown from gate-to-drain using accurate equivalent circuit models

R. T. Cakici, P. E. Nicollian, C. A. Chancellor, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Kaushik Roy, Ashish Goel, Animesh Datta, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks

R. T. Cakici, P. Nicollian, V. Reddy, 2011, IEEE Transactions on Electron Devices.

Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

K. Roy, R. T. Cakici, R.T. Cakici, 2007, IEEE Transactions on Electron Devices.