F. Payet

Using Model for Assessment of Complementary Metal Oxide Semiconductor Technology and Roadmaps as a Pre-Simulation Program with Integrated Circuit Emphasis Model Generator for Early Technology and Circuit Simulation

Frederic Boeuf, Thomas Skotnicki, M. Sellier, 2008 .

Strained-Si for CMOS 65nm node : Si0.8Ge0.2 SRB or “Low Cost” approach ?

C. Laviron, Frederic Boeuf, Yves Campidelli, 2004 .

45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications

Stephane Monfray, Frederic Boeuf, T. Skotnicki, 2005 .

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

V. Fiori, S. Orain, D. Delille, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

T. Skotnicki, C. Ortolland, F. Boeuf, 2008, IEEE Transactions on Electron Devices.

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..