Paul N. Whatmough

发表

Mobile Machine Learning Hardware at ARM: A Systems-on-Chip (SoC) Perspective pdf

Matthew Mattina, Yuhao Zhu, Paul N. Whatmough, 2018, ArXiv.

GeST: An Automatic Framework For Generating CPU Stress-Tests

Shidhartha Das, Yiannakis Sazeides, Paul N. Whatmough, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Selective time borrowing for DSP pipelines with hybrid voltage control loop

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2012, 17th Asia and South Pacific Design Automation Conference.

Guest Editors’ Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning

Yu Cao, Xin Li, Jae-sun Seo, 2019, ACM J. Emerg. Technol. Comput. Syst..

Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators

Gu-Yeon Wei, David M. Brooks, José Miguel Hernández-Lobato, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Sequence-Aware Watermark Design for Soft IP Embedded Processors

Bashir M. Al-Hashimi, Peter R. Wilson, Paul N. Whatmough, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Error-resilient low-power DSP via path-delay shaping

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators

H.-S. Philip Wong, Paul N. Whatmough, Mudit Bhargava, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Hybrid circuit and algorithmic timing error correction for low-power robust DSP accelerators

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster

Shidhartha Das, Paul N. Whatmough, Zacharias Hadjilambrou, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Deep Learning for Computer Architects

Gu-Yeon Wei, David M. Brooks, Robert Adolf, 2017, Synthesis Lectures on Computer Architecture.

SCALE-Sim: Systolic CNN Accelerator pdf

Matthew Mattina, Yuhao Zhu, Paul N. Whatmough, 2018, ArXiv.

Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision

Matthew Mattina, Yuhao Zhu, Paul N. Whatmough, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Applications of Deep Neural Networks for Ultra Low Power IoT

Gu-Yeon Wei, David M. Brooks, Patrick Hansen, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Timing-Error Tolerance Techniques for Low-Power DSP: Filters and Transforms

Paul N. Whatmough, P. Whatmough, 2012 .

Sub-uJ deep neural networks for embedded applications

Gu-Yeon Wei, David M. Brooks, Sae Kyu Lee, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

Precision-energy-throughput scaling of generic matrix multiplication and discrete convolution kernels via linear projections

Yiannis Andreopoulos, Paul N. Whatmough, Mohammad Ashraful Anam, 2013, The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia.

A low-power correlator for wakeup receivers with algorithm pruning through early termination

Andreas Peter Burg, Paul N. Whatmough, Jeremy Constantin, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators

Gu-Yeon Wei, Sae Kyu Lee, Paul N. Whatmough, 2019, 2019 Symposium on VLSI Circuits.

Ares: A framework for quantifying the resilience of deep neural networks

Gu-Yeon Wei, David M. Brooks, Sae Kyu Lee, 2018, Design Automation Conference.

Energy Efficient Hardware for On-Device CNN Inference via Transfer Learning pdf

Patrick Hansen, Matthew Mattina, Paul N. Whatmough, 2018, ArXiv.

A robust FIR filter with in situ error detection

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Precision–Energy–Throughput Scaling of Generic Matrix Multiplication and Convolution Kernels via Linear Projections

Yiannis Andreopoulos, Paul N. Whatmough, Mohammad Ashraful Anam, 2014, IEEE Transactions on Circuits and Systems for Video Technology.

Analysis of adaptive clocking technique for resonant supply voltage noise mitigation

Shidhartha Das, David Michael Bull, Paul N. Whatmough, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

VLSI architecture for a reconfigurable Spectrally Efficient FDM baseband transmitter

Izzat Darwazeh, Paul N. Whatmough, Marcus R. Perrett, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

Izzat Darwazeh, Paul N. Whatmough, Marcus R. Perrett, 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

System-Efficiency Analysis of Power Amplifier Supply-Tracking Regimes in Mobile Transmitters

Paul N. Whatmough, Mark P. van der Heijden, Peter G. Blanken, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET

David Brooks, Gu-Yeon Wei, Patrick Hansen, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications

Gu-Yeon Wei, David M. Brooks, Sae Kyu Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2014, IEEE Journal of Solid-State Circuits.

Error-Resilient Design Techniques for Reliable and Dependable Computing

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2014, IEEE Transactions on Device and Materials Reliability.

A 0.6V all-digital body-coupled wakeup transceiver for IoT applications

Shidhartha Das, Yiannis Andreopoulos, Paul N. Whatmough, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

Shidhartha Das, Paul N. Whatmough, Zacharias Hadjilambrou, 2017, IEEE Journal of Solid-State Circuits.

FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning pdf

Patrick Hansen, Matthew Mattina, Jae-sun Seo, 2019, ArXiv.

ISP4ML: The Role of Image Signal Processing in Efficient Deep Learning Vision Systems

Patrick Hansen, Alexey Vilkin, David Hanwell, 2021, 2020 25th International Conference on Pattern Recognition (ICPR).

S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Acceleration pdf

Matthew Mattina, Yuhao Zhu, Paul N. Whatmough, 2021, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference

Alexander M. Rush, David Brooks, Paul N. Whatmough, 2020, MICRO.

Debiasing Model Updates for Improving Personalized Federated Training

Venkatesh Saligrama, Matthew Mattina, Paul N. Whatmough, 2021, ICML.

Fast and Accurate: Video Enhancement Using Sparse Depth

Patrick Hansen, Yuhao Zhu, Paul N. Whatmough, 2021, 2023 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV).

FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access

Patrick Hansen, Jae-sun Seo, Paul N. Whatmough, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

Doping: A technique for efficient compression of LSTM models using sparse structured additive matrices pdf

Matthew Mattina, Paul N. Whatmough, Jesse Beu, 2021, MLSys.

AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator pdf

S. R. Nandakumar, Irem Boybat, Abu Sebastian, 2021, ArXiv.

9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

Alexander M. Rush, Gu-Yeon Wei, David Brooks, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Federated Learning Based on Dynamic Regularization pdf

Venkatesh Saligrama, Matthew Mattina, Paul N. Whatmough, 2021, ICLR.

Strong data processing inequality in neural networks with noisy neurons and its implications

Matthew Mattina, Paul N. Whatmough, Quntao Zhuang, 2021, 2021 IEEE International Symposium on Information Theory (ISIT).

A LiDAR-Guided Framework for Video Enhancement pdf

Patrick Hansen, Guoyu Lu, Yuhao Zhu, 2021, ArXiv.

Sparse Systolic Tensor Array for Efficient CNN Hardware Acceleration pdf

Matthew Mattina, Paul N. Whatmough, Zhi-Gang Liu, 2020, ArXiv.