Lan-Da Van

发表

Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries

Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, 2013, 2013 9th International Conference on Information, Communications & Signal Processing.

A new VLSI 2-D fourfold-rotational-symmetry filter architecture design

Chin-Teng Lin, Pei-Yu Chen, Lan-Da Van, 2009, 2009 IEEE International Symposium on Circuits and Systems.

High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS

Chien-Ming Wu, Chun-Ming Huang, Jia-Shung Wang, 2005, 2005 IEEE International Conference on Multimedia and Expo.

Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis

Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Qnalyzer: Queuing Recognition Using Accelerometer and Wi-Fi Signals

Yu-Chee Tseng, Lan-Da Van, Cheng-Wei Wu, 2017, GLOBECOM 2017 - 2017 IEEE Global Communications Conference.

New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis

Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Adaptive Low-Error Fixed-Width Booth Multipliers

Sy-Yen Kuo, Lan-Da Van, Min-An Song, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Things in the air: tagging wearable IoT information on drone videos

Lan-Da Van, Yu-Chee Tseng, Kun-Ru Wu, 2020, Discover Internet of Things.

Low complexity subdivision algorithm to approximate Phong shading using forward difference

Lan-Da Van, Cheng-Wei Lin, Ting-Wei Chang, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application

Chin-Teng Lin, Lan-Da Van, Yuan-Chu Yu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters

Wu-Shiung Feng, Lan-Da Van, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)

Lan-Da Van, Chih-Hong Chang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Reconfigurable Depth Buffer Compression Design for 3D Graphics System

Wai-Chi Fang, Lan-Da Van, Teng-Yao Sheu, 2008, 2008 International Conference on Multimedia and Ubiquitous Engineering (mue 2008).

Efficient Detection Algorithms for MIMO Communication Systems

Lan-Da Van, Di-You Wu, 2011, J. Signal Process. Syst..

Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

Lan-Da Van, Jin-Hao Tu, 2009, IEEE Transactions on Computers.

Demo: Tagging IoT Data in a Drone View

Lan-Da Van, Yu-Chee Tseng, Kun-Ru Wu, 2019, MobiCom.

Implementation of a human-centric GUI for next-generation intensive care unit

Lan-Da Van, Shang-Hwa Hsu, Tsung-Che Lu, 2014, 2014 IEEE International Conference on Consumer Electronics - Taiwan.

Intelligent Plant Care Hydroponic Box Using IoTtalk

Yi-Bing Lin, Yun-Wei Lin, Lan-Da Van, 2016, 2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData).

General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry

Chin-Teng Lin, Lan-Da Van, Hari C. Reddy, 2014, Multidimens. Syst. Signal Process..

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Tzyy-Ping Jung, Lan-Da Van, Tsung-Che Lu, 2019, ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

High-speed area-efficient recursive DFT/IDFT architectures

Chih-Chyau Yang, Lan-Da Van, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A Special Section on Advanced Signal Processing Technologies and Systems for Healthcare Applications

Lan-Da Van, Zhiguo Zhang, 2015 .

A generalized methodology for lower-error area-efficient fixed-width multipliers

Lan-Da Van, Sung-Huang Lee, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint

Lan-Da Van, Hari C. Reddy, Chin-Teng Lin, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers

Sy-Yen Kuo, Lan-Da Van, Min-An Song, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis

Chin-Teng Lin, Bor-Chen Kuo, Li-Wei Ko, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

Chin-Teng Lin, Lan-Da Van, Yuan-Chu Yu, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform

Chien-Liang Lin, Pei-Yu Chen, Lan-Da Van, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

A Grouped-Iterative Framework for MIMO Detection

Lan-Da Van, Di-You Wu, 2008, 2008 IEEE 68th Vehicular Technology Conference.

Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry

Chin-Teng Lin, Lan-Da Van, Hari C. Reddy, 2012, 2012 IEEE International Symposium on Circuits and Systems.

FPGA implementation of 4-channel ICA for on-line EEG signal separation

Lan-Da Van, Chin-Teng Lin, Shao-Hang Hung, 2008, 2008 IEEE Biomedical Circuits and Systems Conference.

A low-error and area-time efficient fixed-width booth multiplier

Sy-Yen Kuo, Lan-Da Van, Min-An Song, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System

Lan-Da Van, Teng-Yao Sheu, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

Lan-Da Van, Po-Yen Huang, Tsung-Che Lu, 2016, J. Signal Process. Syst..

New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator

Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design

Chin-Teng Lin, Lan-Da Van, Yuan-Chu Yu, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analyzing students' attention in class using wearable devices

Xin Zhang, Philippe Fournier-Viger, Lan-Da Van, 2017, 2017 IEEE 18th International Symposium on A World of Wireless, Mobile and Multimedia Networks (WoWMoM).

Design of a lower-error fixed-width multiplier for speech processing application

Wu-Shiung Feng, Shing Tenqchen, Shuenn-Shyang Wang, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Green Elevator Scheduling Based on IoT Communications

Tsung-Han Wu, Yi-Bing Lin, Lan-Da Van, 2020, IEEE Access.

A high-performance area-aware DSP processor architecture for video codecs

Chien-Ming Wu, Wei-Chang Tsai, Chun-Ming Huang, 2004, 2004 IEEE International Conference on Multimedia and Expo (ICME) (IEEE Cat. No.04TH8763).

Continuous Human Location and Posture Tracking by Multiple Depth Sensors

Yu-Chee Tseng, Chi-Chung Lo, Yu-Tai Ching, 2014, 2014 IEEE International Conference on Internet of Things(iThings), and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom).

A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage

Wu-Shiung Feng, Lan-Da Van, Chih-Chun Tang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Generalized low-error area-efficient fixed-width multipliers

Chih-Chyau Yang, Lan-Da Van, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping

Lan-Da Van, Ching-Chieh Chiu, Yu-Shu Lin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Hierarchical architecture for network-on-chip platform

Jing-Yang Jou, Lan-Da Van, Cheng-Yeh Wang, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Chin-Teng Lin, Chun-Chieh Huang, Lan-Da Van, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Design of multi-mode depth buffer compression for 3D graphics system

Wai-Chi Fang, Lan-Da Van, Cheng-Wei Lin, 2008, 2008 IEEE International Conference on Multimedia and Expo.

A tree-systolic array of DLMS adaptive filter

Wu-Shiung Feng, Shing Tenqchen, Lan-Da Van, 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

A new VLSI 2-D diagonal-symmetry filter architecture design

Chin-Teng Lin, Pei-Yu Chen, Lan-Da Van, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

An Intelligent Elevator Development and Management System

Yi-Bing Lin, Lan-Da Van, Tsung-Han Wu, 2020, IEEE Systems Journal.

2-D digital filter architectures without global broadcast and some symmetry applications

Chin-Teng Lin, Lan-Da Van, Hari C. Reddy, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Energy-Efficient FastICA Implementation for Biomedical Signal Separation

Lan-Da Van, Di-You Wu, Chien-Shiun Chen, 2011, IEEE Transactions on Neural Networks.

Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures

Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform

Pei-Yu Chen, Lan-Da Van, Shih-Wei Yeh, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

Hardware-efficient architecture design of adaptive visible watermarking

Hen-Wai Tsao, Chun-Ming Huang, Lan-Da Van, 2005, Proceedings of the Ninth International Symposium on Consumer Electronics, 2005. (ISCE 2005)..

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Chien-Ming Wu, Kuen-Jong Lee, Wei-Chang Tsai, 2006, 2006 IEEE International SOC Conference.

A new VLSI architecture without global broadcast for 2-D digital filters

Wu-Shiung Feng, Shing Tenqchen, Lan-Da Van, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A cost-effective reconfigurable accelerator for platform-based SOC design

Chun-Ming Huang, Nien-Hsiang Chang, Lan-Da Van, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications

Chun-Ming Huang, Lan-Da Van, Chi-Sheng Lin, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Anticipatory access pipeline design for phased cache

Chin-Teng Lin, Lan-Da Van, Chih-Wen Hsueh, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A framework for the design of error-aware power-efficient fixed-width Booth multipliers

Sy-Yen Kuo, Chih-Chyau Yang, Lan-Da Van, 2005, 2005 IEEE International Symposium on Circuits and Systems.

PlantTalk: A Smartphone-Based Intelligent Hydroponic Plant Box

Yi-Bing Lin, Yun-Wei Lin, Lan-Da Van, 2019, Sensors.

Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures

Chin-Teng Lin, Pei-Yu Chen, Lan-Da Van, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm

Tzyy-Ping Jung, Lan-Da Van, You-Cheng Tu, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation

Lan-Da Van, Hari C. Reddy, I-Hung Khoo, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

An efficient systolic architecture for the DLMS adaptive filter and its applications

Lan-Da Van, Lan-Da Van, Wu-Shiung Feng, 2001 .

A new 2-D digital filter using a locally broadcast scheme and its cascade form

Shing Tenqchen, Lan-Da Van, Wu-Shiung Feng, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Symmetry Incorporated Cost-Effective Architectures for Two-Dimensional Digital Filters

Pei-Yu Chen, Lan-Da Van, I-Hung Khoo, 2019, IEEE Circuits and Systems Magazine.

Design of the lower error fixed-width multiplier and its application

Lan-Da Van, Lan-Da Van, Wu-Shiung Feng, 2000 .