Atsushi Iwata

发表

Coarse-grain dynamic replication schemes for scalable content delivery networks

Atsushi Iwata, Rauf Izmailov, Norihito Fujita, 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.

A hierarchical multilayer QoS routing system with dynamic SLA management

Atsushi Iwata, Norihito Fujita, A. Iwata, 2000, IEEE Journal on Selected Areas in Communications.

A 60dB SFDR Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

Atsushi Iwata, Kojiro Matsushita, Takafumi Suzuki, 2010 .

Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2004 .

Differential equivalent time sampling receiver for breast cancer detection

Atsushi Iwata, Masahiro Ono, Takamaro Kikkawa, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections

Atsushi Iwata, Junichi Higuchi, Nobuyuki Enomoto, 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2002 .

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique

Atsushi Iwata, Masahiro Ono, Mitsuru Shiozaki, 2005, IEICE Trans. Electron..

Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method

Atsushi Iwata, Takashi Morie, Makoto Nagata, 1998, ICONIP.

Primary low-pass filter

Atsushi Iwata, Takao Kaneko, Hiroyuki Kikuchi, 1980 .

A Multi-Channel Current Stimulator Chip Intended for a Visual Cortical Implant

Atsushi Iwata, Tetsuya Yagi, Dai Akita, 2013 .

A Single-Chip ADM LSI CODEC

Atsushi Iwata, Kuniharu Uchimura, K. Irie, 1983, IEEE Journal of Solid-State Circuits.

High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications

Atsushi Iwata, Junichi Higuchi, Nobuyuki Enomoto, 2008, IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference.

ATM connection and traffic management schemes for multimedia internetworking

Atsushi Iwata, Chinatsu Ikeda, Maximilian Ott, 1995, CACM.

A Feature Associative Processor for Image Recognition Based on A-D merged Architecture

Atsushi Iwata, Takashi Morie, Makoto Nagata, 1999, VLSI.

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications

Atsushi Iwata, Makoto Nagata, Yukihito Kawabe, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Crankback Signaling Extensions for MPLS and GMPLS RSVP-TE

Atsushi Iwata, Adrian Farrel, Norihito Fujita, 2007, RFC.

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality

Atsushi Iwata, Kazuyoshi Takagi, Naofumi Takagi, 2014, 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS).

Building Hierarchical Switch Network Using OpenFlow

Atsushi Iwata, Nobuyuki Enomoto, Hideya Ochiai, 2009, 2009 International Conference on Intelligent Networking and Collaborative Systems.

Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system

Atsushi Iwata, Masahiro Ono, Takamaro Kikkawa, 2017, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Test circuits for substrate noise evaluation in CMOS digital ICs

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2001, ASP-DAC '01.

Scalable routing strategies for ad hoc wireless networks

Atsushi Iwata, Mario Gerla, Ching-Chuan Chiang, 1999, IEEE J. Sel. Areas Commun..

An arbitrary chaos generator core circuit using PWM/PPM signals

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

An Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines.

Atsushi Iwata, Shin Yokoyama, Masataka Hirose, 1998 .

A smart imager for the vision processing front-end

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A 2.0Vpp input, 0.5V supply Delta Amplifier with A-to-D conversion

Atsushi Iwata, Takeshi Yoshida, Yoshihiro Masui, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-/spl mu/s programming time and 11-bit updating resolution

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2001 .

A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations

Atsushi Iwata, Takashi Morie, Masakazu Matsugu, 2005, ICNC.

ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform

Atsushi Iwata, Jun Suzuki, Junichi Higuchi, 2006, 14th IEEE Symposium on High-Performance Interconnects (HOTI'06).

A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture

Atsushi Iwata, Takashi Morie, Hiroshi Ando, 2004, J. Intell. Fuzzy Syst..

Optical interconnection on silicon LSI chips

Atsushi Iwata, Mitsumasa Koyanagi, Yasuhide Kuroda, 1995, Photonics West.

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory

Atsushi Iwata, Takashi Morie, Kan'ya Sasaki, 2006, IEICE Trans. Electron..

The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1999 .

ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks

Atsushi Iwata, Rauf Izmailov, Bhaskar Sengupta, 2000, J. Heuristics.

12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique

Atsushi Iwata, Hiroaki Ikeda, Mitsuru Shiozaki, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

FAM 17.5: A Single-Chip CMOS CODEC with Switched-Capacitor Filters

Atsushi Iwata, Masahiko Nakajima, Hiroyuki Kikuchi, 1980 .

A Neural Recording Amplifier with Low-Frequency Noise Suppression

Atsushi Iwata, Takeshi Yoshida, Masayuki Yoshida, 2010, IEICE Trans. Electron..

A circuit design for sigmoid function generator on APWC circuit

Atsushi Iwata, Tadashi Ae, Keiichi Sakai, 1997 .

Low power and low voltage chopper amplifier without LPF

Atsushi Iwata, Takeshi Yoshida, Yoshihiro Masui, 2008, IEICE Electronics Express.

A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment

Atsushi Iwata, Masaki Aida, Hideyuki Shimonishi, 2011, IEICE Trans. Commun..

Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial

Makoto Nagata, Atsushi Iwata, 2000, ASP-DAC '00.

A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1999 .

Chip-level substrate noise analysis with network reduction by fundamental matrix computation

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

A Stochastic Associative Memory Using Single-Electron Tunneling Devices

Takashi Morie, Makoto Nagata, Atsushi Iwata, 1998 .

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation

Atsushi Iwata, Makoto Nagata, Daisuke Kosaka, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Physical design guides for substrate noise reduction in CMOS digital circuits

Takashi Morie, Makoto Nagata, Atsushi Iwata, 2001 .

Measurements and analyses of substrate noise waveform inmixed-signal IC environment

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A 17 bit oversampling D-A conversion technology using multistage noise shaping

Atsushi Iwata, Takao Kaneko, Y. Matsuya, 1989 .

A 400MSPS 8b flash AD conversion LSI

Atsushi Iwata, Yukio Akazawa, T. Wakimoto, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators

Atsushi Iwata, Toshio Hayashi, Tadakatsu Kimura, 1988, IEEE Trans. Acoust. Speech Signal Process..

A smart imager for the vision processing front-END

Makoto Nagata, Atsushi Iwata, Takashi Morie, 2000, ASP-DAC '00.

Design of multiple reverse spanning trees in next generation of Ethernet-VPNs

Atsushi Iwata, Aleksandar Kolarov, Bhaskar Sengupta, 2004, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04..

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors

Atsushi Iwata, Masahiro Ono, Mitsuru Shiozaki, 2005, J. Robotics Mechatronics.

Substrate crosstalk analysis in mixed signal CMOS integrated circuits

Atsushi Iwata, Makoto Nagata, A. Iwata, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A Nonlinear oscillator network for Gray-level image segmentation and PWM/PPM circuits for its VLSI implementation

Makoto Nagata, Atsushi Iwata, Takashi Morie, 2000 .

A High-Resolution Hadamard Transform Chip

Atsushi Iwata, K. Katayama, A. Iwata, 2002 .

A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC

Atsushi Iwata, Hiroshi Ando, Kunihiko Gotoh, 2009, IEICE Electron. Express.

A study of interference in synchronous systems

Atsushi Iwata, Tsutomu Yoshimura, A. Iwata, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Global open ethernet (GOE) system and its performance evaluation

Atsushi Iwata, Nobuyuki Enomoto, Akira Arutaki, 2004, IEEE Journal on Selected Areas in Communications.

Background Calibration Techniques for Low-Power and High-Speed Data Conversion

Atsushi Iwata, Tomoaki Maeda, Yoshitaka Murasaka, 2011, IEICE Trans. Electron..

Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet

Atsushi Iwata, A. Iwata, 2006, IEICE Trans. Commun..

Quantifying normal and parkinsonian gait features from home movies: Practical application of a deep learning–based 2D pose estimator

Atsushi Iwata, Tatsuo Mano, Tatsushi Toda, 2019, bioRxiv.

A cellular-automaton-type image extraction algorithm and its implementation using an FPGA

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2002, Asia-Pacific Conference on Circuits and Systems.

Stochastic Computing Chip for Measurement of Manhattan Distance

Atsushi Iwata, Michihito Ueda, Michihiro Hori, 2005 .

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Makoto Nagata, Atsushi Iwata, 1999 .

A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique

Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki, 2006, IEICE Trans. Electron..

Neural-processing type optical wavelength demultiplexer using high-speed analog-neural-network integrated circuits

Atsushi Iwata, Yoshihito Amemiya, Akio Sugita, 1991 .

Evaluation of Digital Crosstalk Noise on a Differential Input VCO

Atsushi Iwata, Yoshitaka Murasaka, T. Ohmoto, 2007 .

A high quality ADM LSI codec at 32 kbit/s for digital speech communications

Atsushi Iwata, T. Uno, N. Ohta, 1982, ICASSP.

20GHz uniform-phase uniform-amplitude standing-wave clock distribution

Atsushi Iwata, Mitsuru Shiozaki, Hiroaki Ikeda, 2006, IEICE Electron. Express.

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique

Makoto Nagata, Atsushi Iwata, Takashi Morie, 1999 .

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture

Atsushi Iwata, Takashi Morie, Hiroshi Ando, 2004, KES.

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2001, NIPS.

A nonlinear oscillator network circuit for image segmentation with double-threshold phase detection

Makoto Miyake, Makoto Nagata, Atsushi Iwata, 1999 .

Substrate noise analysis with compact digital noise injection and substrate models

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique

Atsushi Iwata, K. Katayama, A. Iwata, 2003 .

A neural signal detection amplifier with low-frequency noise suppression

Atsushi Iwata, Takeshi Yoshida, Masayuki Yoshida, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A compound-eye imaging module for intraoral biological measurement(Poster session,2nd Asian Image Sensors and Imaging Systems Symposium)

Atsushi Iwata, Keiichiro Kagawa, Jun Tanida, 2014 .

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition

Atsushi Iwata, Takashi Morie, Masakazu Matsugu, 2004, KES.

Off-the-path flow handling mechanism forhigh-speed and programmable traffic management

Atsushi Iwata, Takashi Yoshikawa, Hideyuki Shimonishi, 2008, PRESTO '08.

Adaptive and efficient multiple path pre-computation for QoS routing protocols

Atsushi Iwata, Norihito Fujita, 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

A CMOS Stochastic Associative Processor Using PWM Chaotic Signals

Makoto Nagata, Atsushi Iwata, Takashi Morie, 2001 .

Memory Circuits for PWM signals

Atsushi Iwata, Mokoto Nagata, 1995 .

PCM coder and decoder ICs with switched capacitor filters

Atsushi Iwata, H. Tanaka, M. Ohhata, 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection

Atsushi Iwata, Hiroyuki Ito, Mitsutoshi Sugawara, 2019, 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Low Power 1 GHz Frequency Synthesizer LSI's

Atsushi Iwata, Hiroyuki Kikuchi, Toshiyuki Takahashi, 1983 .

Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection

Atsushi Iwata, Masahiro Ono, Takamaro Kikkawa, 2018, 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS).

FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation

Atsushi Iwata, Takashi Morie, Hiroshi Ando, 2006, Intell. Autom. Soft Comput..

A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion

Atsushi Iwata, Takeshi Yoshida, Yoshihiro Masui, 2009, IEICE Trans. Electron..

Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy

Atsushi Iwata, Tetsuya Yagi, Kazuhiro Shimonomura, 2011, IEEE Transactions on Neural Networks.

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki, 2007, IEICE Trans. Electron..

Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes

Atsushi Iwata, Seiji Kameda, Kan'ya Sasaki, 2006, ACCV.

An analysis of interference in synchronous systems

Atsushi Iwata, Tsutomu Yoshimura, 2004, IEICE Electron. Express.

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2005, J. Robotics Mechatronics.

Stochastic Computing Chip for Measurement of Manhattan Distance

Atsushi Iwata, Michihito Ueda, Michihiro Hori, 2006 .

Gabor-Type Filtering using Transient States of Cellular Neural Networks

Atsushi Iwata, Takashi Morie, Jun Umezawa, 2004, Intell. Autom. Soft Comput..

Coarse-grain replica management strategies for dynamic replication of Web contents

Atsushi Iwata, Rauf Izmailov, Norihito Fujita, 2004, Comput. Networks.

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation

Atsushi Iwata, Takashi Morie, Makoto Nagata, 1998, ICONIP.

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits

Atsushi Iwata, Makoto Nagata, Daisuke Kosaka, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A concept of analog-digital merged circuit architecture for future VLSI's

Makoto Nagata, Atsushi Iwata, 1996 .

DESIGN AND FABRICATION OF OPTICALLY INTERCONNECTED PATTERN RECOGNITION SYSTEM

Makoto Nagata, Atsushi Iwata, Takeshi Doi, 1995 .

Low power PCM CODEC and filter system

Atsushi Iwata, Kuniharu Uchimura, K. Ogasawara, 1981 .

Multilayer In-service Reconfiguration for Network Computing Systems

Atsushi Iwata, Jun Suzuki, Nobuharu Kami, 2007, Sixth IEEE International Symposium on Network Computing and Applications (NCA 2007).

Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies

Makoto Nagata, Atsushi Iwata, Takashi Morie, 2001 .

New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)

Makoto Nagata, Atsushi Iwata, Takashi Morie, 1999 .

A Stochastic Association Circuit Using PWM Chaotic Signals

Makoto Nagata, Atsushi Iwata, Takashi Morie, 1999 .

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Atsushi Iwata, Makoto Nagata, Daisuke Kosaka, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture

Atsushi Iwata, Takashi Morie, Masakazu Matsugu, 2006, IEICE Trans. Electron..

A 1V supply successive approximation ADC with rail-to-rail input voltage range

Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology

Atsushi Iwata, Nobuyuki Enomoto, Daisaku Ogasahara, 2006, IEICE Trans. Commun..

Pulse modulation circuit architecture and its application to functional image sensors

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation

Makoto Miyake, Atsushi Iwata, Takashi Morie, 2001 .

Characteristics of floating gate device as analogue memory for neural networks

Atsushi Iwata, Yoshihito Amemiya, O. Fujita, 1991 .

DESIGN OF A PIXEL-PARALLEL FEATURE EXTRACTION VLSI SYSTEM FOR BIOLOGICALLY-INSPIRED OBJECT RECOGNITION METHODS

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2001 .

Quantum-dot structures measuring Hamming distance for associative memories

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2000 .

Low-Voltage, Low-Phase-Noise Ring-VCO using 1/f-Noise Reduction Techniques

Atsushi Iwata, Takeshi Yoshida, Naoya Ishida, 2006 .

A multi-nano-dot circuit and structure using thermal-noise-assisted tunneling for stochastic associative processing.

Atsushi Iwata, Takashi Morie, Makoto Nagata, 2002, Journal of nanoscience and nanotechnology.