Indrajit Chakrabarti

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Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

Indrajit Chakrabarti, N. Prasad, Santanu Chattopadhyay, 2015, Microprocess. Microsystems.

FPGA implementation of a fetal heart rate measuring system

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2013, 2013 2nd International Conference on Advances in Electrical Engineering (ICAEE).

ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms

Indrajit Chakrabarti, Santanu Chattopadhyay, N. Prasad, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

A novel framework for compressed sensing based scalable video coding

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Vinay Chakravarthi Gogineni, 2017, Signal Process. Image Commun..

VLSI Architecture for Fast Three Step Search Algorithm

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee, 2015 .

High Performance VLSI Architecture for Three-Step Search Algorithm

Indrajit Chakrabarti, Somnath Sengupta, Anindya Sundar Dhar, 2015, Circuits Syst. Signal Process..

Time-frequency masking based supervised speech enhancement framework using fuzzy deep belief network

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2019, Appl. Soft Comput..

Design and evaluation of ZMesh topology for on-chip interconnection networks

Indrajit Chakrabarti, Santanu Chattopadhyay, Priyajit Mukherjee, 2018, J. Parallel Distributed Comput..

A Pipelined Architecture for High Throughput Efficient Turbo Decoder

Indrajit Chakrabarti, S. M. Karim, Girish Mahale, 2011 .

Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems

Indrajit Chakrabarti, Suvra Sekhar Das, Sandip Das, 2015, 2015 Twenty First National Conference on Communications (NCC).

Efficient Pixel Truncation Algorithm and Architecture

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee, 2015 .

Hardware/software co-simulation of entropy coder for compressive sensing based scalable video codec system

Indrajit Chakrabarti, Chandra Prakash, S. N. Karishma, 2017, 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

Indrajit Chakrabarti, Shiju Padmanabhan Puthenpurayil, Rishi Virdi, 2016, IET Circuits Devices Syst..

VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing pdf

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Vinay Chakravarthi Gogineni, 2016, ArXiv.

Improving the Performance of Deep Learning Based Speech Enhancement System Using Fuzzy Restricted Boltzmann Machine

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2017, PReMI.

Programmable Common Baseband Modulator for Software Defined Radio system

Indrajit Chakrabarti, Indranil Hatai, I. Chakrabarti, 2011 .

A probabilistic adaptive algorithm for constructing hierarchical meshes

Indrajit Chakrabarti, Shamik Sural, Kalyan Goswami, 2009, IEEE Transactions on Consumer Electronics.

A new watershed algorithm based on hillclimbing technique for image segmentation

Indrajit Chakrabarti, T. S. Rathore, C. Rambabu, 2003, TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region.

FPGA based architectural implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264/AVC

Indrajit Chakrabarti, Somnath Sengupta, Rohan Mukherjee, 2012 .

Deep Recurrent Neural Network Based Monaural Speech Separation Using Recurrent Temporal Restricted Boltzmann Machines

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2017, INTERSPEECH.

Design of pipelined parallel turbo decoder using contention free interleaver

Indrajit Chakrabarti, S. M. Karim, 2011, TENCON 2011 - 2011 IEEE Region 10 Conference.

Fully automated computer aided diagnosis system for classification of breast mass from ultrasound images

Indrajit Chakrabarti, Poulami Raha, Radhika V. Menon, 2017, 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF

Indrajit Chakrabarti, Rajat Subhra Chakraborty, Pranesh Santikellur, 2019, 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST).

Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application pdf

Indrajit Chakrabarti, Mrigank Sharad, Arindam Basu, 2018, ArXiv.

Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos

Indrajit Chakrabarti, Ajoy Kumar Ray, Rohan Mukherjee, 2016, Microprocess. Microsystems.

Classification of Hand Movements by Surface Myoelectric Signal Using Artificial-Spiking Neural Network Model

Indrajit Chakrabarti, Anand Kumar Mukhopadhyay, Mrigank Sharad, 2018, 2018 IEEE SENSORS.

Design and Implementation of RS (32, 28) Encoder and Decoder Using Cellular Automata

Indrajit Chakrabarti, Dipanwita Roy Chowdhury, Jaydeb Bhaumik, 2007, 15th International Conference on Advanced Computing and Communications (ADCOM 2007).

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

An efficient hardware implementation of DWT and IDWT

Indrajit Chakrabarti, Prabin Kumar Bora, A. S. Motra, 2003, TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region.

A High-Speed FPGA-based Implementation of Inverse Integer Transform Algorithm of H.264

Indrajit Chakrabarti, Ajoy Kumar Ray, Anupam Banerjee, 2017, 2017 14th IEEE India Council International Conference (INDICON).

An efficient VLSI architecture for motion estimation using new three step search algorithm

Indrajit Chakrabarti, Rohan Mukherjee, Baishik Biswas, 2014, TENCON 2014 - 2014 IEEE Region 10 Conference.

A parallel architecture for successive elimination block matching algorithm

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

Design and Implementation of Threshold Logic Functions Using Memristors

Indrajit Chakrabarti, Kamalika Datta, Indranil Sengupta, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Fast One-Bit Transformation Architectures

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee, 2015 .

Modelling of Cooperative Spectrum Sensing over Rayleigh Fading Without CSI in Cognitive Radio Networks

Debasish Bera, Indrajit Chakrabarti, Sant Saran Pathak, 2016, Wirel. Pers. Commun..

A high-speed, ROM-less DDFS for software defined radio system

Indrajit Chakrabarti, Indranil Hatai, 2010, 2010 INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES.

Two-Stage Temporal Processing for Single-Channel Speech Enhancement

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2016, INTERSPEECH.

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

Indrajit Chakrabarti, S. M. Karim, Shaikh Montajul Karim, 2012, IET Commun..

Design and implementation of error correcting codes and cryptographic primitives

Indrajit Chakrabarti, Dipanwita Roy Chowdhury, Jaydeb Bhaumik, 2010 .

High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000

Indrajit Chakrabarti, Sumit Kumar Chatterjee, Tenugu Suman, 2008, 2008 Sixth Indian Conference on Computer Vision, Graphics & Image Processing.

High speed VLSI architecture for improved region based active contour segmentation technique

Indrajit Chakrabarti, Radhika V. Menon, Shantharam Kalipatnapu, 2021, Integr..

A Parallel Stochastic Number Generator With Bit Permutation Networks

Indrajit Chakrabarti, N. Prasad, Vikash Sehwag, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

FPGA Implementation of a Digital FM Modem

Indrajit Chakrabarti, Indranil Hatai, 2009, 2009 International Conference on Information and Multimedia Technology.

Another Look in the Analysis of Cooperative Spectrum Sensing over Nakagami- $m$ Fading Channels

Debasish Bera, Indrajit Chakrabarti, George K. Karagiannidis, 2015, IEEE Transactions on Wireless Communications.

Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning

Indrajit Chakrabarti, Anindya Sundar Dhar, Mamata Panigrahy, 2016 .

VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm

Indrajit Chakrabarti, Shiju Padmanabhan Puthenpurayil, Rishi Virdi, 2018, Microprocess. Microsystems.

A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS

Indrajit Chakrabarti, Indranil Hatai, 2011 .

An improved low-power high-throughput log-MAP turbo decoder

Indrajit Chakrabarti, Shaikh Montajul Karim, 2010, IEEE Transactions on Consumer Electronics.

A phase-aware single channel speech enhancement technique using separate bayesian estimators for voiced and unvoiced regions with digital hearing aid application

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2015, 2015 17th International Conference on E-health Networking, Application & Services (HealthCom).

Design and implementation of a generalized parametrizable modulator for a reconfigurable radio

Indrajit Chakrabarti, Saswat Chakrabarti, Jagadeesh Gurugubelli, 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation

Indrajit Chakrabarti, Anindya Sundar Dhar, Rohan Mukherjee, 2016, J. Circuits Syst. Comput..

VLSI Architecture for Enhanced Approximate Message Passing Algorithm

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Kota Naga Srinivasaro Batta, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

Speech enhancement based on modulation domain processing using coherent harmonic demodulation technique

Indrajit Chakrabarti, Suman Samui, Soumya K. Ghosh, 2017 .

High performance VLSI implementation of CAVLC decoder of H.264/AVC for HD transmission

Indrajit Chakrabarti, Somnath Sengupta, Rohan Mukherjee, 2013, 2013 Annual IEEE India Conference (INDICON).

Introduction to Scalable Image and Video Coding

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee, 2015 .

Parameter controlled reconfigurable baseband modulator for SDR architecture

Indrajit Chakrabarti, Indranil Hatai, I. Chakrabarti, 2010, 2010 2nd International Conference on Mechanical and Electronics Engineering.

Efficient architecture of adaptive rood pattern search technique for fast motion estimation

Indrajit Chakrabarti, Rohan Mukherjee, Baishik Biswas, 2015, Microprocess. Microsystems.

VLSI design of fast fractal image encoder

Indrajit Chakrabarti, Anindya Sundar Dhar, Mamata Panigrahy, 2014, 18th International Symposium on VLSI Design and Test.

A high performance VLSI architecture for Fast Two-Step Search algorithm for sub-pixel motion estimation

Indrajit Chakrabarti, Sumit K. Chatterjee, 2009, 2009 International Multimedia, Signal Processing and Communication Technologies.

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Power efficient motion estimation algorithm and architecture based on pixel truncation

Indrajit Chakrabarti, Sumit Kumar Chatterjee, 2011, IEEE Transactions on Consumer Electronics.

High Speed VLSI Architecture for 3-D Discrete Wavelet Transform pdf

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, 2015, ArXiv.

An Improved Double Byte Error Correcting Code Using Cellular Automata

Indrajit Chakrabarti, Dipanwita Roy Chowdhury, Jaydeb Bhaumik, 2008, ACRI.

Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application pdf

Indrajit Chakrabarti, Anand Kumar Mukhopadhyay, Mrigank Sharad, 2019, ArXiv.

High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Mohammad Nawaz Ahmad, 2015, IET Circuits Devices Syst..

Hardware implementation of quadtree based fractal image decoder

Indrajit Chakrabarti, Anindya Sundar Dhar, Mamata Panigrahy, 2016, 2016 Twenty Second National Conference on Communication (NCC).

Compressive sensing based scalable video coding for space applications

Indrajit Chakrabarti, S. N. Karishma, B. K. N. Srinivasarao, 2016, 2016 Twenty Second National Conference on Communication (NCC).

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder

Indrajit Chakrabarti, Anindya Sundar Dhar, Mamata Panigrahy, 2017, VDAT.

Hardware implementation of MIMO OFDMA test bed and its application towards channel characterization on indoor LAB test environment

Indrajit Chakrabarti, Suvra Sekhar Das, Sandip Das, 2016, 2016 Twenty Second National Conference on Communication (NCC).

Complexity assisted consistent quality rate control for high resolution H.264 video conferencing

Indrajit Chakrabarti, Maheshkumar H. Kolekar, Subhomoy Bhattacharyya, 2015, 2015 Fifth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG).

Runtime mitigation of illegal packet request attacks in Networks-on-Chip

Indrajit Chakrabarti, Santanu Chattopadhyay, Rajit Karmakar, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of efficient high throughput pipelined parallel turbo decoder using QPP interleaver

Indrajit Chakrabarti, S. M. Karim, 2011, 2011 International Conference on Multimedia, Signal Processing and Communication Technologies.

Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2016, IET Signal Process..

A Fast and Low-power VLSI Architecture for Half-pixel Motion Estimation Using Two-step Search Algorithm for HDTV Application

Indrajit Chakrabarti, Sumit K. Chatterjee, 2011 .

High-performance compensation technique for the radix-4 CORDIC algorithm

Indrajit Chakrabarti, P. R. Rao, I. Chakrabarti, 2002 .

An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture

Indrajit Chakrabarti, Santanu Chattopadhyay, N. Prasad, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

VLSI architecture of forward and inverse quantization modules of H.264 for HD transmission

Indrajit Chakrabarti, Somnath Sengupta, Rohan Mukherjee, 2013, 2013 Annual IEEE India Conference (INDICON).

High performance VLSI architecture for 3-D discrete wavelet transform

Indrajit Chakrabarti, B. K. N. Srinivasarao, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An efficient FPGA based implementation of forward integer transform and quantization algorithm of H.264

Indrajit Chakrabarti, Ajoy Kumar Ray, Anupam Banerjee, 2016, 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER).

Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter

Indrajit Chakrabarti, Arijit De, Sudipta Bose, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC

Indrajit Chakrabarti, Ashish Singhadia, Pratik Bante, 2019, IEEE Transactions on Consumer Electronics.

Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos

Indrajit Chakrabarti, Ajoy Kumar Ray, Priyabrata Saha, 2018, Expert Syst. Appl..

Automated detection and classification of mass from breast ultrasound images

Indrajit Chakrabarti, Rezaul Karim, Sumit Chakraborty, 2015, 2015 Fifth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG).

An efficient watershed transform computation method

Indrajit Chakrabarti, C. Rambabu, D. Ghosh, 2003, Fourth International Conference on Information, Communications and Signal Processing, 2003 and the Fourth Pacific Rim Conference on Multimedia. Proceedings of the 2003 Joint.

Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices

Indrajit Chakrabarti, Ashish Singhadia, Meghan Mamillapalli, 2020, IEEE Transactions on Consumer Electronics.

Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing

Indrajit Chakrabarti, Shantharam Kalipatnapu, I. Chakrabarti, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-throughput Bit Flipping decoder for structured LDPC codes

Indrajit Chakrabarti, Shantharam Kalipatnapu, 2019, IET Commun..

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

Indrajit Chakrabarti, Priyabrata Saha, Rohan Mukherjee, 2016 .

Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code

Indrajit Chakrabarti, Dipanwita Roy Chowdhury, Jaydeb Bhaumik, 2010, ACRI.

A novel low-latency, high-speed DDFS architecture

Indrajit Chakrabarti, Indranil Hatai, 2010, 2010 Annual IEEE India Conference (INDICON).

Classification of breast mass in ultrasound images using CAD: A survey

Indrajit Chakrabarti, Poulami Raha, Radhika V. Menon, 2016, 2016 International Conference on Systems in Medicine and Biology (ICSMB).

Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm

Indrajit Chakrabarti, D. Ghosh, P. N. Swamy, 2002 .

Hexagon Based Compressed Diamond Algorithm for motion estimation and its dedicated VLSI system for HD videos

Indrajit Chakrabarti, Rohan Mukherjee, Ajoy Kumar Ray, 2020, Expert Syst. Appl..

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip pdf

Indrajit Chakrabarti, Santanu Chattopadhyay, Navonil Chatterjee, 2019, ArXiv.

Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of $$512 \times 512$$512×512 Frames

Indrajit Chakrabarti, Ajoy Kumar Ray, Somnath Sengupta, 2017, Circuits Syst. Signal Process..

Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

Hardware Implementation of Compressed Sensing based Low Complex Video Encoder pdf

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, I. Chakrabarti, 2015, ArXiv.

Multi-standard programmable baseband modulator for next generation wireless communication pdf

Indrajit Chakrabarti, Indranil Hatai, I. Chakrabarti, 2010, ArXiv.

Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications

Indrajit Chakrabarti, Mrigank Sharad, Anand Kumar Mukhopadhyay, 2017, 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

FPGA Implementation of a Phase-Aware Single-Channel Speech Enhancement System

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2017, Circuits Syst. Signal Process..

Algorithm and architecture for quarter pixel motion estimation for H.264/AVC

Indrajit Chakrabarti, Sumit K. Chatterjee, 2013, 2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG).

Tensor-Train Long Short-Term Memory for Monaural Speech Enhancement pdf

Indrajit Chakrabarti, Soumya K. Ghosh, Suman Samui, 2018, ArXiv.

Low-Delay Parallel Architecture for Fractal Image Compression

Indrajit Chakrabarti, Anindya Sundar Dhar, Mamata Panigrahy, 2015, Circuits, Systems, and Signal Processing.

Flooding-based watershed algorithm and its prototype hardware architecture

Indrajit Chakrabarti, C. Rambabu, A. Mahanta, 2004 .

Hardware implementation of MIL-STD-1553 protocol over OFDMA-PHY based wireless high data rate avionics systems

Indrajit Chakrabarti, Suvra Sekhar Das, Sandip Das, 2016, 2016 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS).

Low power VLSI architectures for one bit transformation based fast motion estimation

Indrajit Chakrabarti, Sumit Kumar Chatterjee, 2010, IEEE Transactions on Consumer Electronics.

Motion Estimation for Video Coding - Efficient Algorithms and Architectures

Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee, 2015, Studies in Computational Intelligence.

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

Indrajit Chakrabarti, Indranil Hatai, 2011, Int. J. Reconfigurable Comput..

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm

Indrajit Chakrabarti, Ajoy Kumar Ray, Rohan Mukherjee, 2018, Circuits Syst. Signal Process..

Efficient VLSI design of CAVLC decoder of H.264 for HD videos

Indrajit Chakrabarti, Ajoy Kumar Ray, Rohan Mukherjee, 2017, 2017 7th International Symposium on Embedded Computing and System Design (ISED).

NoC Based Multiplier-Less Constant Geometry FFT Architecture

Indrajit Chakrabarti, Santanu Chattopadhyay, N. Prasad, 2014, 2014 Fourth International Conference of Emerging Applications of Information Technology.

Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier

Indrajit Chakrabarti, Mrigank Sharad, Arindam Basu, 2021, ACM J. Emerg. Technol. Comput. Syst..

Embedding delay-based physical unclonable functions in networks-on-chip

Indrajit Chakrabarti, Santanu Chattopadhyay, Vikash Sehwag, 2021, IET Circuits Devices Syst..

A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC

Indrajit Chakrabarti, Ashish Singhadia, Meghan Mamillapalli, 2021 .

Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array

Indrajit Chakrabarti, Anand Kumar Mukhopadhyay, Sampurna Majumder, 2022, Comput. Electr. Eng..

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Indrajit Chakrabarti, Sudipta Bose, Arijit De, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Global soft decision based speech enhancement using voiced-unvoiced uncertainty and harmonic phase decomposition technique

Indrajit Chakrabarti, Suman Samui, Soumya Kanti Ghosh, 2016, 2016 International Conference on Signal Processing and Communications (SPCOM).

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC

Indrajit Chakrabarti, Indranil Hatai, Swapna Banerjee, 2015 .