Giuseppe Ascia

发表

A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers

Alessandro G. Di Nuovo, Giuseppe Ascia, 2013, J. Intell. Fuzzy Syst..

Design of a VLSI hardware PET decoder

Vincenzo Catania, Giuseppe Ficili, Giuseppe Ascia, 1997, Proceedings Tenth International Conference on VLSI Design.

A Reconfigurable Parallel Architecture for a Fuzzy Processor

Antonio Puliafito, Vincenzo Catania, Giuseppe Ascia, 1996, Inf. Sci..

A new selection policy for adaptive routing in network on chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2006 .

Design space exploration methodologies for IP-based system-on-a-chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Exploring design space of VLIW architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

VLSI hardware architecture for complex fuzzy systems

Vincenzo Catania, Giuseppe Ascia, Marco Russo, 1999, IEEE Trans. Fuzzy Syst..

An integrated fuzzy-GA approach for buffer management

Daniela Panno, Vincenzo Catania, Giuseppe Ascia, 2006, IEEE Transactions on Fuzzy Systems.

A data dependent model for software power estimation: Un modello dipendente dai dati per la valutazione del consumo di potenza

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2001 .

An efficient buffer management policy based on an integrated fuzzy-GA approach

Daniela Panno, Vincenzo Catania, Giuseppe Ascia, 2002, Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies.

A framework for design space exploration of parameterized VLSI systems

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Hyperblock formation: a power/energy perspective for high performance VLIW architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005, 2005 IEEE International Symposium on Circuits and Systems.

An Instruction-Level Power Analysis Model with Data Dependency

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2001, VLSI Design.

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

Daniela Panno, Vincenzo Catania, Maurizio Palesi, 2015, J. Comput. Sci..

Design of a VLSI fuzzy processor for ATM traffic sources management

Daniela Panno, Giuseppe Ficili, Giuseppe Ascia, 1995, Proceedings of 20th Conference on Local Computer Networks.

A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems

Vincenzo Catania, Alessandro G. Di Nuovo, Giuseppe Ascia, 2012, PPSN.

A GA-based design space exploration framework for parameterized system-on-a-chip platforms

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2004, IEEE Transactions on Evolutionary Computation.

An evolutionary approach to network-on-chip mapping problem

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005, 2005 IEEE Congress on Evolutionary Computation.

Design of a VLSI parallel processor for fuzzy computing

Vincenzo Catania, Giuseppe Ascia, 1995, Proceedings of the 8th International Conference on VLSI Design.

An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning

Vincenzo Catania, Giuseppe Ascia, 1996, Int. J. Artif. Intell. Tools.

Switching activity reduction in embedded systems: a genetic bus encoding approach

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, Lecture Notes in Computer Science.

Low Energy Mapping Techniques under Reliability and Bandwidth Constraints

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2013, 2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing.

An encoding scheme to reduce power consumption in Networks-on-Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2009, 2009 International Conference on Computer Engineering & Systems.

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices

John Jose, Salvatore Monteleone, Vincenzo Catania, 2019, 2019 Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS).

A dedicated parallel processor for fuzzy computation

Vincenzo Catania, Giuseppe Ascia, 1997, Proceedings of 6th International Fuzzy Systems Conference.

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2008, IEEE Transactions on Computers.

An adaptive fuzzy threshold scheme for high performance shared-memory switches

Daniela Panno, Vincenzo Catania, Giuseppe Ascia, 2001, SAC.

Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems

Alessandro Di Nuovo, Vincenzo Catania, Maurizio Palesi, 2008 .

Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression

Salvatore Monteleone, Vincenzo Catania, Maurizio Palesi, 2020, 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

Parameterised system design based on genetic algorithms

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2001, CODES '01.

Exploiting antenna directivity in wireless NoC architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2016, Microprocess. Microsystems.

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A framework for a parallel architecture dedicated to soft computing

Vincenzo Catania, Giuseppe Ascia, 1998, Proceedings Eleventh International Conference on VLSI Design.

Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A general purpose processor oriented to fuzzy reasoning

Vincenzo Catania, Giuseppe Ascia, V. Catania, 2001, 10th IEEE International Conference on Fuzzy Systems. (Cat. No.01CH37297).

NoC links energy reduction through link voltage scaling

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2013, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

A fuzzy buffer management scheme for ATM and IP networks

Daniela Panno, Vincenzo Catania, Giuseppe Ficili, 2001, Proceedings IEEE INFOCOM 2001. Conference on Computer Communications. Twentieth Annual Joint Conference of the IEEE Computer and Communications Society (Cat. No.01CH37213).

A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2006, J. Univers. Comput. Sci..

An Optimized Parallel RISC Processor for Fuzzy Computing

Vincenzo Catania, Giuseppe Ascia, 1999, Applied Informatics.

An evolutionary approach for reducing the energy in address buses

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, ISICT.

Runtime Online Links Voltage Scaling for Low Energy Networks on Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2013, 2013 Euromicro Conference on Digital System Design.

Fuzzy decision making in embedded system design

Vincenzo Catania, Maurizio Palesi, Alessandro G. Di Nuovo, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, PATMOS.

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005, ASP-DAC.

Mapping Cores on Network-on-Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005 .

Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection

Giuseppe Pappalardo, Andrea Fornaia, Emiliano Tramontana, 2016, 2016 IEEE 25th International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE).

Efficient design space exploration for application specific systems-on-a-chip

Vincenzo Catania, Maurizio Palesi, Alessandro G. Di Nuovo, 2007, J. Syst. Archit..

A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design

Vincenzo Catania, Maurizio Palesi, Alessandro G. Di Nuovo, 2006, 2006 IEEE International Conference on Evolutionary Computation.

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.

A VLSI fuzzy expert system for real-time traffic control in ATM networks

Daniela Panno, Sergio Palazzo, Vincenzo Catania, 1997, IEEE Trans. Fuzzy Syst..

A VLSI Parallel Architecture for Fuzzy Expert Systems

Vincenzo Catania, Giuseppe Ascia, 1995, Int. J. Pattern Recognit. Artif. Intell..

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2001, VLSI-SOC.

Fuzzy Hardware Challenges

Abraham Kandel, Yoichi Miyake, Antonio Ruiz, 1995, IEEE Micro.

DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators

Salvatore Monteleone, Vincenzo Catania, Jordane Lorandel, 2020, 2020 23rd Euromicro Conference on Digital System Design (DSD).

Tuning Methodologies for Parameterized Systems Design

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003 .

An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design

Vincenzo Catania, Maurizio Palesi, Alessandro G. Di Nuovo, 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An efficient hardware architecture to support complex fuzzy reasoning

Vincenzo Catania, Giuseppe Ascia, 1995, Proceedings of 7th IEEE International Conference on Tools with Artificial Intelligence.

Exploiting Data Resilience in Wireless Network-on-chip Architectures

John Jose, Salvatore Monteleone, Vincenzo Catania, 2020, ACM J. Emerg. Technol. Comput. Syst..

Data Encoding Schemes in Networks on Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving energy consumption of NoC based architectures through approximate communication

John Jose, Salvatore Monteleone, Vincenzo Catania, 2018, 2018 7th Mediterranean Conference on Embedded Computing (MECO).

EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, ESTImedia.

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems

Vincenzo Catania, Maurizio Palesi, Alessandro G. Di Nuovo, 2011, Appl. Soft Comput..

Design issues of an asynchronous parallel fuzzy processor

Vincenzo Catania, Giuseppe Ascia, Lorenzo Vita, 1995, Proceedings of 1995 IEEE International Conference on Fuzzy Systems..

A Genetic Approach To Bus Encoding

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, VLSI-SOC.

An evolutionary management scheme in high-performance packet switches

Daniela Panno, Vincenzo Catania, Giuseppe Ascia, 2005, IEEE/ACM Transactions on Networking.

Multi-objective mapping for mesh-based NoC architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An evolutionary approach for reducing the switching activity in address buses

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2003, The 2003 Congress on Evolutionary Computation, 2003. CEC '03..

Multiobjective optimization of a parameterized VLIW architecture

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2004, Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004..

Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression

John Jose, Salvatore Monteleone, Vincenzo Catania, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling

Partha Pratim Pande, Vincenzo Catania, Maurizio Palesi, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2013, 2013 Euromicro Conference on Digital System Design.

Approximate Wireless Networks-on-Chip

John Jose, Salvatore Monteleone, Vincenzo Catania, 2018, 2018 Conference on Design of Circuits and Integrated Systems (DCIS).

Designing for parallel fuzzy computing

Vincenzo Catania, Giuseppe Ascia, Lorenzo Vita, 1995, IEEE Micro.

A Closed Loop Control based Power Manager for WiNoC Architectures

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2014, MES '14.

Rule-Driven VLSI Fuzzy Processor

Vincenzo Catania, Giuseppe Ascia, Lorenzo Vita, 1996 .

Analyzing networks-on-chip based deep neural networks

John Jose, Salvatore Monteleone, Vincenzo Catania, 2019, NOCS.

A CLOSED LOOP POWER MANAGER FOR TRANSMISSION POWER CONTROL IN WIRELESS NETWORK-ON-CHIP ARCHITECTURES

Vincenzo Catania, Maurizio Palesi, Giuseppe Ascia, 2015 .

A parallel processor architecture for real-time fuzzy applications

Vincenzo Catania, Giuseppe Ascia, V. Catania, 1997 .

LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation

Salvatore Monteleone, Vincenzo Catania, Maurizio Palesi, 2021, 2021 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops).

DNN Model Compression for IoT Domain-Specific Hardware Accelerators

Salvatore Monteleone, Vincenzo Catania, Maurizio Palesi, 2022, IEEE Internet of Things Journal.