Anup Dandapat

发表

Design of 64-Bit Squarer Based on Vedic Mathematics

Deepak Kumar, Prabir Saha, Partha Bhattacharyya, 2014, J. Circuits Syst. Comput..

A Novel Methodology for Design of Cyclic Combinational Circuits

Chandan Kumar Jha, Vinay Kumar, Anup Dandapat, 2016, J. Low Power Electron..

Design of a high performance memory using a novel architecture of double bit CAM and SRAM

Chandan Kumar Sarkar, Anup Dandapat, D. Kayal, 2012 .

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, Microelectron. J..

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

Deepak Kumar, Anup Dandapat, Prabir Saha, 2017 .

Precharge free dynamic content addressable memory

Anup Dandapat, Sheikh Wasmir Hussain, Telajala Venkata Mahendra, 2018 .

Improved matrix multiplier design for high-speed digital signal processing applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2014, IET Circuits Devices Syst..

Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage

Anup Dandapat, Sandeep Mishra, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control

Anup Dandapat, Sandeep Mishra, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style

Chandan Kumar Jha, Anup Dandapat, Gaurav Thapa, 2016 .

Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique

Vinay Kumar, Anup Dandapat, A. Dandapat, 2016, J. Circuits Syst. Comput..

Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory

Anup Dandapat, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, 2018, IEEE Transactions on Consumer Electronics.

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access

Anup Dandapat, Sandeep Mishra, Venkatesh Mani Tripathi, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2011, 2011 International Symposium on Electronic System Design.

Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM

Anup Dandapat, D. Kayal, D. Mukhopadhyay, 2008, J. Low Power Electron..

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme

Anup Dandapat, Telajala Venkata Mahendra, Sandeep Mishra, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Proposed thesis title "Implementation of the Computational Arithmetic Operations for Signal Processing Applications"

Deepak Kumar, Anup Dandapat, 2014 .

ASIC implementation of high speed processor for calculating discrete Fourier transformation using circular convolution technique

Prabir Saha, Partha Bhattacharyya, Anup Dandapat, 2011 .

Low Power and High Speed Factorial Design in 22 nm Technology

Anup Dandapat, Arindam Banerjee, Prabir Kumar Saha, 2010 .

A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications

Anup Dandapat, Telajala Venkata Mahendra, Sandeep Mishra, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design of High Speed Vedic Multiplier for Decimal Number System

Arindam Banerjee, Prabir Saha, Partha Bhattacharyya, 2012, VDAT.

Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

Anup Dandapat, Sandeep Mishra, Telajala Venkata Mahendra, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique

Chandan Kumar Sarkar, Anup Dandapat, Posiba Mostafa, 2014, J. Signal Process. Syst..

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Vinay Kumar, Partha Bhattacharyya, Anup Dandapat, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique

Partha Bhattacharyya, Anup Dandapat, D. Ghosh, 2013, J. Low Power Electron..

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications

Deepak Kumar, Prabir Saha, Partha Bhattacharyya, 2013, 2013 International Symposium on Electronic System Design.

Match-line control unit for power and delay reduction in hybrid CAM

Anup Dandapat, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, 2021, IET Circuits Devices Syst..

Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors

Prabir Saha, Anup Dandapat, Arindam Banerjee, 2011 .

HIGH SPEED MULTIPLIER USING HIGH ACCURACY OATING POINT LOGARITHMIC NUMBER SYSTEM

Prabir Saha, Anup Dandapat, Arindam Banerjee, 2014 .