S. Maitrejean

发表

Highly automated sequence for Phase Change Memory test structure characterization

G. Reimbold, B. DeSalvo, J. Cluzel, 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

An application of carbon nanotubes for integrated circuit interconnects

S. Maitrejean, J. C. Coiffic, L. E. Foa Torres, 2008, NanoScience + Engineering.

Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs

M. Vinet, S. Deleonibus, M. Mouis, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Emerging memory technologies: Challenges and opportunities

B. DeSalvo, V. Jousseaume, E. Vianello, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

D. Delille, T. Skotnicki, F. Leverd, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Trade-off between SET and data retention performance thanks to innovative materials for phase-change memory

G. Reimbold, P. Zuliani, A. Cabrini, 2013, 2013 IEEE International Electron Devices Meeting.

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

M. Vinet, L. Grenouillet, Y. Morand, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Carbon-doped GeTe Phase-Change Memory featuring remarkable RESET current reduction

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

Toward the integration of a single carbon nanofibre as via interconnect

H. Le Poche, Nicolas Chevalier, S. Maitrejean, 2008 .

Understanding CMP-induced delamination in ultra low-k/Cu integration

V. Jousseaume, D. Scevola, P. Leduc, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

Integrating of Cu/SiOC in Cu dual damascene interconnect for 0.1-µm technology

Pascal Besson, Gilles L. Fanget, Lucile Arnaud, 2002 .

Three dimensional chip stacking using a wafer-to-wafer integration

N. Kernevez, M. Zussy, Zhihong Huang, 2007, 2007 IEEE International Interconnect Technology Conferencee.

Challenges for 3D IC integration: bonding quality and thermal management

N. Kernevez, M. Zussy, F. de Crecy, 2007, 2007 IEEE International Interconnect Technology Conferencee.

On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 IEEE International Memory Workshop.

Lowering the Reset Current and Power Consumption of Phase-Change Memories with Carbon-Doped Ge2Sb2Te5

G. Reimbold, P. Zuliani, G. Pananakakis, 2012, 2012 4th IEEE International Memory Workshop.

N-doped GeTe as performance booster for embedded Phase-Change Memories

G. Reimbold, D. Blachier, A. Toffoli, 2010, 2010 International Electron Devices Meeting.

Metal gate and high-k integration for advanced CMOS devices

Thomas Skotnicki, Sorin Cristoloveanu, Simon Deleonibus, 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..

Electrical Performances of Tellurium-Rich GexTe1-x Phase Change Memories

P. Zuliani, G. Navarro, A. Toffoli, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Breakthroughs in 3D Sequential technology

X. Garros, P. Batude, M. Vinet, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).