Hendrawan Soeleman

Robust ultra-low power sub-threshold DTMOS logic

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Robust subthreshold logic for ultra-low power operation

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Ultra-low power digital subthreshold logic circuits

Kaushik Roy, Hendrawan Soeleman, K. Roy, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Ultra -low power digital sub-threshold logic design

Hendrawan Soeleman, 2000 .

The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1997 .

Ultra-low-power DLMS adaptive filter for hearing aid applications

Kaushik Roy, Hendrawan Soeleman, Chris Hyung-Il Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Estimating Circuit Activity in Combinational CMOS Digital Circuits

Kaushik Roy, Tan-Li Chou, Hendrawan Soeleman, 2000, IEEE Des. Test Comput..

An 8×8 sub-threshold digital CMOS carry save array multiplier

Kaushik Roy, Bipul C. Paul, Hendrawan Soeleman, 2001 .

Digital CMOS logic operation in the sub-threshold region

Kaushik Roy, Hendrawan Soeleman, 2000, ACM Great Lakes Symposium on VLSI.