Bipul Chandra Paul

发表

Robust ultra-low power sub-threshold DTMOS logic

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Robust subthreshold logic for ultra-low power operation

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Enhancing yield at the end of the technology roadmap

Kaushik Roy, Bipul Chandra Paul, Naran Sirisantana, 2004, IEEE Design & Test of Computers.

Adaptive supply voltage technique for low swing interconnects

Kaushik Roy, Bipul Chandra Paul, Woopyo Jeong, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Device optimization for ultra-low power digital sub-threshold operation

Kaushik Roy, Arijit Raychowdhury, Bipul Chandra Paul, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Low-power design techniques for scaled technologies

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2006, Integr..

Impact of body bias on delay fault testing of nanoscale CMOS circuits

Kaushik Roy, Bipul Chandra Paul, Cassondra Neau, 2004, 2004 International Conferce on Test.

Circuit Failure Prediction and Its Application to Transistor Aging

Ming Zhang, Bipul Chandra Paul, Subhasish Mitra, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Prospect of ballistic CNFET in high performance applications: Modeling and analysis

Shinobu Fujita, Bipul Chandra Paul, Thomas Lee, 2007, JETC.

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory

Rolf Drechsler, Chip-Hong Chang, Chulwoo Kim, 2019, IEEE Trans. Very Large Scale Integr. Syst..

Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis

Kaushik Roy, Bipul Chandra Paul, 2002, Proceedings. International Test Conference.

ROM based logic (RBL) design: High-performance and low-power adders

Shinobu Fujita, Bipul Chandra Paul, Masaki Okajima, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges

Arijit Raychowdhury, Bipul Chandra Paul, 2011, Low-Power Variation-Tolerant Design in Nanometer Silicon.

Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]

Kaushik Roy, Bipul Chandra Paul, Seung Hoon Choi, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Introduction to the special issue on memory technologies

Arijit Raychowdhury, Bipul Chandra Paul, 2013, JETC.

Design verification and robust design technique for cross-talk faults

Kaushik Roy, Bipul Chandra Paul, Yonghee Im, 2001, Proceedings 10th Asian Test Symposium.

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

Kaushik Roy, Bipul Chandra Paul, Aditya Bansal, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Process variation in nano-scale memories: failure analysis and process tolerant architecture

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Modeling and analysis of circuit performance of ballistic CNFET

Shinobu Fujita, Bipul Chandra Paul, Thomas Lee, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A process-tolerant cache architecture for improved yield in nanoscale technologies

Kaushik Roy, Amit Agarwal, Animesh Datta, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Novel sizing algorithm for yield improvement under process variation in nanometer technology

Kaushik Roy, Bipul Chandra Paul, Seung Hoon Choi, 2004, Proceedings. 41st Design Automation Conference, 2004..

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, TODE.

Advances in nanoelectronics circuits and systems [Editorial]

Krishnendu Chakrabarty, Bipul Chandra Paul, 2009, IET Comput. Digit. Tech..

Statistical timing analysis using levelized covariance propagation

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2005, Design, Automation and Test in Europe.

A Retrospective View on the Technology Evolution to Support Low Power Mobile Application

Edward J. Nowak, Lars Liebmann, Bipul Chandra Paul, 2018, J. Low Power Electron..

Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Optimized Circuit Failure Prediction for Aging: Practicality and Promise

Bo Yang, Yu Cao, Wenping Wang, 2008, 2008 IEEE International Test Conference.

A novel fault tolerant cache to improve yield in nanometer technologies

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.