Sam-Young Bang

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Woo-Jin Lee, Young-Hyun Jun, Jeong-Don Ihm, 2008, IEEE Journal of Solid-State Circuits.

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Young-Hyun Jun, Jeong-Don Ihm, Seung-Jun Bae, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.