Juinn-Dar Huang

发表

ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication

Jing-Yang Jou, Bu-Ching Lin, Juinn-Dar Huang, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1995, ICCAD.

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

Yen-Ting Lin, Jing-Yang Jou, Juinn-Dar Huang, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips

Chia-Hung Liu, Juinn-Dar Huang, Huei-Shan Lin, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FSM-Based Formal Compliance Verification of Interface Protocols

Chia-Chih Yen, Jing-Yang Jou, Juinn-Dar Huang, 2010, J. Inf. Sci. Eng..

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1996, ICCAD 1996.

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Juinn-Dar Huang, Ya-Shih Huang, Juinn-Dar Huang, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models

Juinn-Dar Huang, Kang-Yi Fan, Shigeru Yamashita, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Verification of Pin-Accurate Port Connections

Jing-Yang Jou, Chun-Yao Wang, Juinn-Dar Huang, 2008, IEEE Design & Test of Computers.

Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip

Yi-Ling Chen, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2018, ACM Trans. Embed. Comput. Syst..

Two-staged parallel layer-aware partitioning for 3D designs

Yi-Ting Chen, Juinn-Dar Huang, Yi-Hang Chen, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Verification on port connections

Jing-Yang Jou, Chun-Yao Wang, Juinn-Dar Huang, 2004, 2004 International Conferce on Test.

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models

Chia-Hung Liu, Juinn-Dar Huang, Kuo-Cheng Shen, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Microarchitecture-Aware Floorplanning for Processor Performance Optimization

Hung-Ming Chen, Juinn-Dar Huang, Chi-Ying Chen, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1996, Proceedings of International Conference on Computer Aided Design.

TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance

Juinn-Dar Huang, Ya-Shih Huang, Han-Yuan Chang, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

Jing-Yang Jou, Bu-Ching Lin, Juinn-Dar Huang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Throughput-a ware floorplanning via dynamic optimization on performancecritical loops

Liya Wang, Juinn-Dar Huang, Ya Shih Huang, 2010 .

Cycle-time-aware sequential way-access set-associative cache for low energy consumption

Juinn-Dar Huang, Yu-Hsiang Kao, Chih-Hui Ting, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Yen-Ting Lin, Juinn-Dar Huang, Chia-I Chen, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Latency-optimization synthesis with module selection for digital microfluidic biochips

Chia-Hung Liu, Juinn-Dar Huang, Kuang-Cheng Liu, 2013, 2013 IEEE International SOC Conference.

Reactant cost minimization through target concentration selection on microfluidic biochips

Yi-Ling Chen, Juinn-Dar Huang, Yung-Chun Lei, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme

Yi Lu, Juinn-Dar Huang, Yi-Lin Wu, 2020, ISCAS.

Throughput optimization for latency-insensitive system with minimal queue insertion

Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Juinn-Dar Huang, Jian-Yu Chen, Yi-Hang Chen, 2014, DATE 2014.

Sample preparation for droplet-based microfluidics

Chia-Hung Liu, Juinn-Dar Huang, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Input Selection Encoding for Low Power Multiplexer Tree

Juinn-Dar Huang, Chia-I Chen, Hsiao-En Chang, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

Jing-Yang Jou, Juinn-Dar Huang, Chien-Hua Chen, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing

Juinn-Dar Huang, Wei-Sheng Huang, Ya-Shih Huang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Reducing fault dictionary size for million-gate large circuits

Juinn-Dar Huang, Yu-Ru Hong, Juinn-Dar Huang, 2009, TODE.

Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees

Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models

Juinn-Dar Huang, Yung-Chun Lei, Tung-Hsuan Lin, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

Low-Power Instruction Cache Architecture Using Pre-Tag Checking

Juinn-Dar Huang, Shi-You Cheng, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays

Yang Chen, Juinn-Dar Huang, Yi-Hang Chen, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture

Juinn-Dar Huang, Ya-Shih Huang, Yu-Ju Hong, 2009, 2009 Asia and South Pacific Design Automation Conference.

Defect-aware synthesis for reconfigurable single-electron transistor arrays

Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Expandable MDC-based FFT architecture and its generator for high-performance applications

Jing-Yang Jou, Yu-Hsiang Wang, Bu-Ching Lin, 2010, 23rd IEEE International SOC Conference.

Architectural exploration of 3D FPGAs towards a better balance between area and delay

Juinn-Dar Huang, Chia-I Chen, Bau-Cheng Lee, 2011, 2011 Design, Automation & Test in Europe.

Property/Assertion Based Verification

Juinn-Dar Huang, 2004 .

CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Juinn-Dar Huang, Chia-I Chen, 2009, 2009 Asia and South Pacific Design Automation Conference.

Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

Jing-Yang Jou, Juinn-Dar Huang, Chia-I Chen, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Juinn-Dar Huang, Jian-Yu Chen, Yi-Hang Chen, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays

Chia-Cheng Wu, Chun-Yao Wang, Juinn-Dar Huang, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips

Sudip Roy, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family

Juinn-Dar Huang, Chia-I Chen, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips

Juinn-Dar Huang, Yung-Chun Lei, Ling-Yen Song, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)

Juinn-Dar Huang, Ya-Shih Huang, Han-Yuan Chang, 2012, FPGA '12.

Formal compliance verification of interface protocols

Chia-Chih Yen, Jing-Yang Jou, Juinn-Dar Huang, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

A Comprehensive Security System for Digital Microfluidic Biochips

Tsung-Yi Ho, Hailong Yao, Juinn-Dar Huang, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers

Chia-Hung Liu, Juinn-Dar Huang, Chi-Mei Huang, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

FSM-based transaction-level functional coverage for interface compliance verification

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping

Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao, 1995, 32nd Design Automation Conference.

Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip

Robert Wille, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization

Yi Lu, Juinn-Dar Huang, Yi-Lin Wu, 2020, 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

High-performance NAND flash controller exploiting parallel out-of-order command execution

Juinn-Dar Huang, Yu-Hsiang Kao, Juinn-Dar Huang, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing

Chia-Hung Liu, Juinn-Dar Huang, Tung-Che Liang, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors

Jing-Yang Jou, Bu-Ching Lin, Juinn-Dar Huang, 2014, J. Inf. Sci. Eng..

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

Jing-Yang Jou, Juinn-Dar Huang, Che-Hua Shih, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

On circuit clustering for area/delay tradeoff under capacity and pin constraints

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs

Juinn-Dar Huang, Yi-Ling Chen, Yung-Chun Lei, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

Verification on port connections

Jing-Yang Jou, Chun-Yao Wang, Juinn-Dar Huang, 2004 .

BDD based lambda set selection in Roth-Karp decomposition for LUT architecture

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Performance-optimal behavioral synthesis with degenerable compound functional units

Juinn-Dar Huang, Yi-Hang Chen, Wan-Hsien Lin, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture

Juinn-Dar Huang, Ya-Shih Huang, Yu-Ju Hong, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips

Juinn-Dar Huang, Yung-Chun Lei, Tien-Kuo Lin, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips

Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Layer-Aware Design Partitioning for Vertical Interconnect Minimization

Juinn-Dar Huang, Ya-Shih Huang, Yang-Hsiang Liu, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Efficient two-layered cycle-accurate modeling technique for processor family with same instruction set architecture

Juinn-Dar Huang, Chien-De Chiang, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Compatible class encoding in hyper-function decomposition for FPGA synthesis

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Chain-based pin count minimization for general-purpose digital microfluidic biochips

Jing-Yang Jou, Juinn-Dar Huang, Yung-Chun Lei, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Fault Dictionary Size Reduction for Million-Gate Large Circuits

Juinn-Dar Huang, Yu-Ru Hong, Juinn-Dar Huang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration

Tsung-Yi Ho, Paul Pop, Juinn-Dar Huang, 2013, 2013 IEEE International SOC Conference.

Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip

Robert Wille, Bhargab B. Bhattacharya, Juinn-Dar Huang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low power multiplexer tree design using dynamic propagation path control

Juinn-Dar Huang, Han-Jung Huang, Nan-Shing Li, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device--Based Biochips

Ankur Gupta, Sudip Roy, Juinn-Dar Huang, 2019, ACM Trans. Design Autom. Electr. Syst..

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication

Juinn-Dar Huang, Chia-I Chen, Juinn-Dar Huang, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Unified functional decomposition via encoding for FPGA technology mapping

Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks pdf

Juinn-Dar Huang, Cheng-Wei Huang, Tim-Wei Chen, 2021, ArXiv.

Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip

Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips

Juinn-Dar Huang, Chih-Shen Yeh, Ling-Yen Song, 2021, 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing

Juinn-Dar Huang, Ya-Chu Chang, Wei-Chen Lin, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model

Chia-Cheng Wu, Juinn-Dar Huang, Chia-Chun Lin, 2021, ACM J. Emerg. Technol. Comput. Syst..

Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation

Jing-Yang Jou, Juinn-Dar Huang, Ling-Yen Song, 2021 .