Mitsuho Seki

A practical clock router that accounts for the capacitance derived from parallel and cross segments

Kazuo Kato, Mitsuho Seki, S. Kobayashi, 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

Design of a 200MHz 1.2W 1.4GFLOPS Processor with Graphic Floating-point Extension

Tetsuya Yamada, Norio Nakagawa, Hideo Maejima, 1998 .

A new floorplan simultaneously placing blocks over two logic layers for sea-of-gate gate arrays

Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Timing-oriented routers for PCB layout design of high-performance computers

Terumine Hayashi, Masahiro Takakura, Mitsuho Seki, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

A specified delay accomplishing clock router using multiple layers

Kenji Inoue, Kazuo Kato, Mitsuho Seki, 1994, ICCAD.

Design methodology of a 200 MHz superscalar macroprocessor: SH-4

Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).