文
论文分享
演练场
杂货铺
论文推荐
字
编辑器下载
登录
注册
W. Dally
发表
A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips
R. Farjad-Rad, R. Rathi, J. Poulton, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).