D. Sylvester

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

J.C. Chen, S.-Y. Oh, D. Sylvester, 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling

Chenming Hu, D. Sylvester, T. Sato, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

J.C. Chen, Chenming Hu, D. Sylvester, 1997, IEEE Electron Device Letters.

Switch-factor based loop RLC modeling for efficient timing analysis

Yu Cao, D. Sylvester, Xiaodong Yang, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Process variability-aware transient fault modeling and analysis

Cheng Zhuo, D. Sylvester, D. Blaauw, 2008, ICCAD 2008.