Dong-Woo Jee

发表

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform

David Blaauw, Dennis Sylvester, Jae-Yoon Sim, 2015, IEEE Journal of Solid-State Circuits.

A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

Jae-Yoon Sim, Hong-June Park, Yunjae Suh, 2011, 2011 IEEE International Solid-State Circuits Conference.

A low-voltage OP amp with digitally controlled algorithmic approximation

Jae-Yoon Sim, Hong-June Park, Seungjin Park, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2013, IEEE Journal of Solid-State Circuits.

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

Refet Firat Yazicioglu, Rachit Mohan, Julia Pettine, 2015, IEEE Journal of Solid-State Circuits.

A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms

David Blaauw, Dennis Sylvester, Jae-Yoon Sim, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC

Jae-Yoon Sim, Hong-June Park, Dong-Woo Jee, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC

Hong-June Park, Jae-Yoon Sim, Yunjae Suh, 2016, J. Circuits Syst. Comput..

Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System

Dong-Woo Jee, Kyu-Jin Choi, 2021, IEEE Transactions on Instrumentation and Measurement.

A 0.052 mm2, <0.4% THD, Sinusoidal Current Generator for Bio-Impedance Measurement Using a Recursive Digital Oscillator and Current-Domain FIR Filter

Dong-Woo Jee, Seok-Ki Hong, Dong-Woo Jee, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Robust high-multiplication factor MDLL using IIR filter-based accumulated jitter reduction

Dong-Woo Jee, 2018 .

Current/Voltage Dual-Mode Single-Wire Simultaneous Bidirectional Interface Architecture for Sensor System

Dong-Woo Jee, Jeong-Kyun Kim, 2020, IEEE Transactions on Biomedical Circuits and Systems.

A Multi(bio)sensor Acquisition System With Integrated Processor, Power Management, $8 \times 8$ LED Drivers, and Simultaneously Synchronized ECG, BIO-Z, GSR, and Two PPG Readouts

Refet Firat Yazicioglu, Julia Pettine, Mario Konijnenburg, 2016, IEEE Journal of Solid-State Circuits.

A <25 μW CMOS monolithic photoplethysmographic sensor with distributed 1b delta-sigma light-to-digital convertor

Dong-Woo Jee, Hyung-Gi Kim, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

Phase-blender-based FIR noise filtering techniques for ΔΣ fractional-N PLL

Jae-Yoon Sim, Hong-June Park, Yunjae Suh, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction

Dong-Woo Jee, Jinseop Noh, 2019, IEICE Electron. Express.

A 13 $\mu {\rm A}$ Analog Signal Processing IC for Accurate Recognition of Multiple Intra-Cardiac Signals

Refet Firat Yazicioglu, Julia Pettine, Yasunari Harada, 2013, IEEE Transactions on Biomedical Circuits and Systems.

A 1.9 ㎓ Fractional-N Digital PLL with Sub-Exponent ΔΣ TDC

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2012 .

A 8 GByte/s transceiver with current-balanced pseudo-differential signaling for memory interface

Hong-June Park, Yunjae Suh, Dong-Woo Jee, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance

Junil Choi, In-Soo Kim, Youngjoo Lee, 2019, IEEE Access.

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ \Delta\Sigma$ TDC and IIR-Based Noise Cancellation

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Two-step injection clock generation technique for fractional- N MDLL

Dong-Woo Jee, 2016 .

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2015 .

A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation.

Jae-Yoon Sim, Hong-June Park, Dong-Woo Jee, 2012 .

Fractional-N multiplying delay-locked loop with delay-locked loop-based injection clock generation

Dong-Woo Jee, 2016 .

Embedded Phase-Interpolator-Based Noise Filtering

Jae-Yoon Sim, Hong-June Park, Yunjae Suh, 2011 .