D. Deschacht

发表

On-chip crosstalk evaluation between adjacent interconnections

G. Servel, D. Deschacht, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

On the analysis of four symmetrical interconnects for signal integrity evaluation

D. Deschacht, F. Ponchel, J.F. Legier, 2005, Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005..

RLC crosstalk calculation with dissymmetrical attacks

D. Deschacht, J.E. Lorival, 2007, 2007 IEEE Workshop on Signal Propagation on Interconnects.

Victim andaggressor line electrical modelisation inanmulticoupled interconnect environment fortransient simulation

D. Deschacht, F. Ponchel, E. Paleczny, 2006 .

Respective parts of capacitive and inductive coupling

D. Deschacht, 2005, Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005..

Full Wave Analysis and Electrical Modeling of Eight Copper Interconnects Placed in a Giga-Scale Integrated Environment for Signal Integrity Evaluation

D. Deschacht, F. Ponchel, J.F. Legier, 2006, 2006 1st Electronic Systemintegration Technology Conference.

Illustration of the importance of on-chip self and mutual inductances

D. Deschacht, A. Lopez, D. Deschacht, 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

Proximity Effect ofNeighbour Victim Lossy Interconnects onaSingle Attacker andViceVersa

D. Deschacht, F. Ponchel, E. Paleczny, 2012 .

Delay-time evaluation in ED MOS logic LSI

D. Deschacht, Daniel Auvergne, Michel Robert, 1986 .

Impact of inductance and routing orientation on timing performances of coupled interconnect lines

D. Deschacht, D. Deschacht, 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Accurate modeling of interconnections for timing simulation of sub-micronic circuits

D. Deschacht, E. Vanier, D. Deschacht, 1998 .

Optimum repeater insertion to minimize the propagation delay into 32nm RLC interconnect

D. Deschacht, 2011, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

Keep on shrinking interconnect size: Is it still the best solution?

D. Deschacht, A. Farcy, T. Lacrevaz, 2010, 2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT).

Crosstalk pulsewidth calculation

D. Deschacht, Jean-Etienne Lorival, 2008, DTIS 2008.

Parasitic influence, on signal integrity, of several victim lines placed asymmetrically beside and symmetrically at both sides of an attacker interconnect and mutually

D. Deschacht, F. Ponchel, J.F. Legier, 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

Analytical crosstalk noise characteristics

D. Deschacht, J.E. Lorival, 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Design of an integrated programmable neurostimulator

D. Deschacht, D. Auvergne, M. Robert, 1990, [Proceedings] EURO ASIC `90.

Benefit on interconnect performance of a relaxed wire density in a 45 nm node of the Back End of Line

D. Deschacht, A. Farcy, T. Lacrevaz, 2010, 2010 IEEE 14th Workshop on Signal Propagation on Interconnects.

Capacitive and inductive couplings in a distributed RLC interconnection line system: Additivity waveforms

D. Deschacht, Y. Quere, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

A full-wave analysis of submicronic circuits in the microwave frequency range to estimate the input shape influence over VLSI interconnect performances

G. Servel, D. Deschacht, E. Paleczny, 1999 .

Full Wave Analysis of Conductor and Substrate Losses in High Speed VLSI Interconnects

G. Servel, D. Deschacht, P. Kennis, 2000, 2000 30th European Microwave Conference.

Input waveform slope effects in CMOS delays

D. Deschacht, Michel Robert, Daniel Auvergne, 1990 .

Evaluation of VLSI layout style implementations for efficiency

D. Deschacht, N. Azemard, D. Auvergne, 1991, Euro ASIC '91.

Inductance effect for interconnection timing analysis in submicronic circuits

G. Servel, D. Deschacht, E. Paleczny, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Impact of Low-K Intra-layer Dielectrics on Integration

D. Deschacht, F. Huret, 2002, Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects.

TVA: A timing verifier with analytic temporal modelling

D. Deschacht, D. Auvergne, D. Navarro, 1991 .

Inductance effect in crosstalk prediction

G. Servel, D. Deschacht, Fabrice Huret, 2002 .

Explicit formulation of delays in CMOS data paths

D. Deschacht, Michel Robert, Daniel Auvergne, 1988 .

13th IEEE Workshop on SIGNAL PROPAGATION ON INTERCONNECTS.

E. Griese, D. Deschacht, R. Abhari, 2009 .

Interconnect Pitch for New Generation: Evolution due to Inductive Impact

D. Deschacht, T. Le Gouguec, J.E. Lorival, 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

Interconnect design for a 32 nm node technology

D. Deschacht, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Victim and aggressor line electrical modelisation in an multicoupled interconnect environment for transient simulation

D. Deschacht, F. Ponchel, J.F. Legier, 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

Explicit formulation of delays in CMOS VLSI

D. Deschacht, Daniel Auvergne, Michel Robert, 1987 .

FullWaveAnalysis andElectrical Modeling ofEightCopperInterconnects Placed ina Giga-Scale Integrated Environment forSignal Integrity Evaluation

D. Deschacht, E. Paleczny, C. Seguinot, 2006 .

Effective interconnect networks design in CMOS 45 nm circuits to joint reductions of XT and delay for transmission of very high speed signals

D. Deschacht, A. Farcy, T. Lacrevaz, 2010, 2010 IEEE Electrical Design of Advanced Package & Systems Symposium.

Theoretical analysis of signal reflections on Cu on-chip interconnections

G. Servel, D. Deschacht, E. Paleczny, 2000 .

RLC Interconnect Crosstalk Waveform Evaluation

D. Deschacht, J.E. Lorival, 2007, 2007 International Symposium on Integrated Circuits.

A Numerical Method for a Full-Wave Electromagnetic Analysis of Systems on Chip

D. Deschacht, T. Le Gouguec, P. M. Martin, 2003, 2003 33rd European Microwave Conference, 2003.

Synchronous-mode evaluation of delays in CMOS structures

D. Deschacht, Michel Robert, Daniel Auvergne, 1991 .

Delay propagation effect in transistor gates

D. Deschacht, D. Auvergne, C. Dabrin, 1996 .

Impact of inductance on timing characteristics of VLSI interconnects

G. Servel, D. Deschacht, P. Kennis, 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).

Coupled line modelization of lossy adjacent interconnects with a full wave tangential vector finite element method

G. Servel, D. Deschacht, E. Paleczny, 2001 .

Input Shape Influence over Interconnect Performances

G. Servel, D. Deschacht, E. Paleczny, 2000 .

Inductive effects on crosstalk evaluation

G. Servel, D. Deschacht, E. Paleczny, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Electrical performance of single and coupled Cu interconnects for the 70 nm technology

D. Deschacht, E. Paleczny, C. Seguinot, 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

Additivity of capacitive and inductive coupling in submicronic interconnects

D. Deschacht, T. Le Gouguec, F. Huret, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Inductance effect in interconnect coupling noise

D. Deschacht, E. Paleczny, Fabrice Huret, 2001 .