Tsutomu Sasao

发表

Representations of logic functions using QRMDDs

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.

A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions

Tsutomu Sasao, 1991, [1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic.

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

A regular expression matching using non-deterministic finite automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroshi Nakahara, 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, ISMVL.

Calculation of Reed-Muller-Fourier coefficients of multiple-valued functions through multiple-place decision diagrams

Claudio Moraga, Radomir S. Stankovic, Tsutomu Sasao, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).

A set partition number system

Tsutomu Sasao, Jon T. Butler, 2016, Australas. J Comb..

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables

Tsutomu Sasao, Munehiro Matsuura, Takaaki Nakamura, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A Quaternary Decision Diagram Machine and the Optimization of its Code

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2009, 2009 39th International Symposium on Multiple-Valued Logic.

An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division

Tsutomu Sasao, Hiroki Nakahara, Hiroyuki Nakanishi, 2017, CARN.

Arithmetic Ternary Decision Diagrams Applications and Complexity

Tsutomu Sasao, Tsutomu Sasao, 1999 .

Design Methods for Multiple-Valued Input Address Generators

Tsutomu Sasao, 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2015, IEICE Trans. Inf. Syst..

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2010, IEICE Trans. Inf. Syst..

On the minimization of average path lengths for heterogeneous MDDs [multi-valued decision diagrams]

Shinobu Nagayama, Tsutomu Sasao, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays

Tsutomu Sasao, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

A fast segmentation algorithm for piecewise polynomial numeric function generators

Tsutomu Sasao, Jon T. Butler, C. L. Frenzen, 2011, J. Comput. Appl. Math..

Cascade Realization of 3-Input 3-Output Conservative Logic Circuits

Kozo Kinoshita, Tsutomu Sasao, 1978, IEEE Transactions on Computers.

Head-Tail Expressions for Interval Functions

Tsutomu Sasao, Infall Syafalni, Tsutomu Sasao, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, J. Multiple Valued Log. Soft Comput..

A method to represent multiple-output switching functions by using multi-valued decision diagrams

Tsutomu Sasao, Jon T. Butler, 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

A Regular Expression Matching Circuit Based on a Decomposed Automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2011, ARC.

EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, J. Multiple Valued Log. Soft Comput..

Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation

Tsutomu Sasao, 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

Analysis of Multi-state Systems with Multi-state Components Using EVMDDs

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

Index Generation Functions: Tutorial

Tsutomu Sasao, 2014, J. Multiple Valued Log. Soft Comput..

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope

Tsutomu Sasao, Hiroki Nakahara, Naoya Ogawa, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

A simplification method for AND-EXOR expressions for multiple-output functions

Tsutomu Sasao, Norio Koda, 1996, Systems and Computers in Japan.

Representations of Elementary Functions Using Binary Moment Diagrams

Shinobu Nagayama, Tsutomu Sasao, 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

A heuristic algorithm to design AND-OR-EXOR three-level networks

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Approach to design a compact reversible low power binary comparator

Tsutomu Sasao, Hafiz Md. Hasan Babu, Nazir Saleheen, 2014, IET Comput. Digit. Tech..

Radix converters: complexity and implementation by LUT cascades

Tsutomu Sasao, 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams

Tsutomu Sasao, Hafiz Md. Hasan Babu, 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

An Architecture for IPv6 Lookup Using Parallel Index Generation Units

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, ARC.

Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions

Tsutomu Sasao, Jon T. Butler, Robert J. Barton, 1997, IEEE Trans. Computers.

An FPGA design of AES encryption circuit with 128-bit keys

Tsutomu Sasao, Yukihiro Iguchi, Hui Qin, 2005, ACM Great Lakes Symposium on VLSI.

On the Numbers of Products in Prefix SOPs for Interval Functions

Tsutomu Sasao, Infall Syafalni, 2013, IEICE Trans. Inf. Syst..

An Efficient Heuristic for Linear Decomposition of Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

Planarity in ROMDDs of multiple-valued symmetric functions

Tsutomu Sasao, Jon T. Butler, J. L. Nowlin, 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

Comparison of the worst and best sum-of-products expressions for multiple-valued functions

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 1997, Proceedings 1997 27th International Symposium on Multiple- Valued Logic.

A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs

Tsutomu Sasao, 2017, IEICE Trans. Inf. Syst..

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, J. Multiple Valued Log. Soft Comput..

A hardware simulation engine based on decision diagrams (short paper)

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, ASP-DAC '00.

A Quaternary Decision Diagram Machine: Optimization of Its Code

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2010, IEICE Trans. Inf. Syst..

MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators

Tsutomu Sasao, 1986, 23rd ACM/IEEE Design Automation Conference.

A virus scanning engine using a parallel finite-input memory machine and MPUs

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A Packet Classifier Using Parallel EVMDD (k) Machine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 IEEE 7th International Symposium on Embedded Multicore Socs.

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, J. Multiple Valued Log. Soft Comput..

Inadmissible Class of Boolean Functions under Stuck-at Faults

Tsutomu Sasao, Bhargab B. Bhattacharya, Debesh Kumar Das, 2013, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

Index Generation Functions: Recent Developments

Tsutomu Sasao, Tsutomu Sasao, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

On the optimization of heterogeneous MDDs

Shinobu Nagayama, Tsutomu Sasao, S. Nagayama, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Publications in the First Twenty Years of Switching Theory and Logic Design

Jaakko Astola, Tsutomu Sasao, J. Astola, 2001 .

Complexities of Graph-Based Representations for Elementary Functions

Shinobu Nagayama, Tsutomu Sasao, Tsutomu Sasao, 2009, IEEE Transactions on Computers.

Programmable Numerical Function Generators for Two-Variable Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions

Tsutomu Sasao, Debatosh Debnath, 1995, ASP-DAC '95.

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

Selection of potentially testable path delay faults for test generation

Irith Pomeranz, Sudhakar M. Reddy, Tsutomu Sasao, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

An Exact Method to Enumerate Decomposition Charts for Index Generation Functions

Tsutomu Sasao, Jon T. Butler, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).

A Realization of Index Generation Functions Using Multiple IGUs

Tsutomu Sasao, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

Compact representations of logic functions using heterogeneous MDDs

Shinobu Nagayama, Tsutomu Sasao, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

On the numbers of variables to represent sparse logic functions

Tsutomu Sasao, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Large-scale SOP minimization using decomposition and functional properties

Tsutomu Sasao, Alan Mishchenko, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2007, 2007 Asia and South Pacific Design Automation Conference.

Paper Special Section on Vlsi Design and Cad Algorithms Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 2022 .

On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions

Tsutomu Sasao, 2010, DSD 2010.

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2017, IEICE Trans. Inf. Syst..

A Method to Realize Logic Functions using LUTs and OR Gates

Tsutomu Sasao, Munehiro Matsuura, Tsutomu Sasao, 2003 .

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA

Tsutomu Sasao, Yukihiro Iguchi, Hui Qin, 2006, IEICE Trans. Inf. Syst..

Design Methods of Radix Converters Using Arithmetic Decompositions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, IEICE Trans. Inf. Syst..

Worst and Best Irredundant Sum-of-Products Expressions

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2001, IEEE Trans. Computers.

A memory-based realization of a binarized deep convolutional neural network

Tsutomu Sasao, Hiroki Nakahara, Masato Motomura, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Logic Synthesis and Optimization

Tsutomu Sasao, Tsutomu Sasao, 1997 .

Fast Hardware Computation of x Mod z

Tsutomu Sasao, Jon T. Butler, 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

An optimization of AND-OR-EXOR three-level networks

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions

Tsutomu Sasao, 2017, J. Multiple Valued Log. Soft Comput..

Design of Address Generators Using Multiple LUT Cascade on FPGA

Tsutomu Sasao, Hui Qin, 2006 .

On the design of LPM address generators using multiple LUT cascades on FPGAs

Tsutomu Sasao, Jon T. Butler, Hui Qin, 2007 .

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, Microprocess. Microsystems.

A Fast Head-Tail Expression Generator for TCAM -- Application to Packet Classification

Tsutomu Sasao, Infall Syafalni, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, J. Multiple Valued Log. Soft Comput..

Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers

Tsutomu Sasao, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM

Tsutomu Sasao, Infall Syafalni, Xiaoqing Wen, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Packet Classifier Using a Parallel Branching Program Machine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Planar multiple-valued decision diagrams

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 1995, Proceedings 25th International Symposium on Multiple-Valued Logic.

Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation

Tsutomu Sasao, 2013, J. Multiple Valued Log. Soft Comput..

Average path length of binary decision diagrams

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2005, IEEE Transactions on Computers.

On properties of Kleene TDDs

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Realization of multiple-output functions by reconfigurable cascades

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

A Parallel Branching Program Machine for Emulation of Sequential Circuits

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, ARC.

On LUT cascade realizations of FIR filters

Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Numerical Function Generators Using LUT Cascades

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2007, IEEE Transactions on Computers.

A Design Method for AND-OR-EXOR Three-Level Networks

Tsutomu Sasao, 1995 .

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

On a wideband fast fourier transform for a radio telescope

Tsutomu Sasao, Hiroki Nakahara, Hiroyuki Nakanishi, 2012, CARN.

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

Tsutomu Sasao, Debatosh Debnath, 2005, IEICE Trans. Inf. Syst..

On the properties of multiple-valued functions that are symmetric in both variable values and labels

Tsutomu Sasao, Jon T. Butler, 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).

An evaluation system for logic functions based on decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2004 .

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, IEICE Trans. Inf. Syst..

Multiple-valued minimization to optimize PLAs with output EXOR gates

Tsutomu Sasao, Debatosh Debnath, 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

Tsutomu Sasao, Tsutomu Sasao, 1981, IEEE Transactions on Computers.

Signal Processing and System Design of Cylinder Reliability Test for ISO Standard

Tsutomu Sasao, 2010, 2010 International Conference on Electrical and Control Engineering.

Design Methods for Multi-Rail Cascades

Tsutomu Sasao, 2002 .

Programmable numerical function generators: architectures and synthesis method

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2005, International Conference on Field Programmable Logic and Applications, 2005..

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2006 .

Decision diagrams for discrete functions: classification and unified interpretation

Radomir S. Stankovic, Tsutomu Sasao, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Hardware to compute Walsh coefficients

Tsutomu Sasao, Yukihiro Iguchi, 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

Numerical function generators using bilinear interpolation

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2009, 2009 39th International Symposium on Multiple-Valued Logic.

Minimization of memory size for heterogeneous MDDs

Shinobu Nagayama, Tsutomu Sasao, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions

Tsutomu Sasao, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs

Tsutomu Sasao, 1985, IEEE Transactions on Computers.

A discussion on the history of research in arithmetic andReed-Muller expressions

Radomir S. Stankovic, Tsutomu Sasao, Tsutomu Sasao, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2005, J. Multiple Valued Log. Soft Comput..

Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions

Tsutomu Sasao, Debatosh Debnath, 2000, ASP-DAC.

On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults

Tsutomu Sasao, Bhargab B. Bhattacharya, Debesh Kumar Das, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

Conservative Logic Elements and Their Universality

Kozo Kinoshita, Tsutomu Sasao, K. Kinoshita, 1979, IEEE Transactions on Computers.

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank

Tsutomu Sasao, Hiroki Nakahara, Hideki Yoshida, 2015, ARC.

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades

Tsutomu Sasao, Munehiro Matsuura, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A fast method to derive minimum SOPs for decomposable functions

Tsutomu Sasao, Jon T. Butler, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Four-variable AND-EXOR minimum expressions and their properties

Tsutomu Sasao, Norio Koda, 1992, Systems and Computers in Japan.

Bi-Partition of Shared Binary Decision Diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2002 .

Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions

Tsutomu Sasao, Alan Mishchenko, 2002 .

Delay and Asynchronous Behavior

Tsutomu Sasao, 1999 .

Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

Progress in Applications of Boolean Functions

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2010, Progress in Applications of Boolean Functions.

A Packet Classifier Based on Prefetching EVMDD (k) Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, IEICE Trans. Inf. Syst..

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, ARC.

Hahoe KAIST Robot Theatre: learning rules of interactive robot behavior as a multiple-valued logic synthesis problem

Tsutomu Sasao, Martin Lukac, Jong-Hwan Kim, 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

Evaluation of multiple-output logic functions using decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2003, ASP-DAC '03.

Numeric Function Generators Using Piecewise Arithmetic Expressions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector

Tsutomu Sasao, Hiroki Nakahara, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

On Magnetic Bubble Logic Circuits

Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda, 1976, IEEE Transactions on Computers.

On the Optimal Design of Multiple-Valued PLA's

Tsutomu Sasao, 1989, IEEE Trans. Computers.

A packet classifier using LUT cascades based on EVMDDS (k)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables

Tsutomu Sasao, 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

Easily Testable Realizations for Generalized Reed-Muller Expressions

Tsutomu Sasao, 1997, IEEE Trans. Computers.

Reeducation for Design Engineers in Fukuoka System LSI College

Akira Fukuda, Tsutomu Sasao, Kazuyuki Hirakawa, 2012 .

Cascade realizations of two-valued input multiple-valued output functions using decomposition of group functions

Tsutomu Sasao, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators

Shinobu Nagayama, Tsutomu Sasao, Tsutomu Sasao, 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer

Tsutomu Sasao, Hiroki Nakahara, Hiroyuki Nakanishi, 2012, ICA3PP.

Easily Testable Sequential Machines with Extra Inputs

Kozo Kinoshita, Tsutomu Sasao, Hideo Fujiwara, 1975, IEEE Transactions on Computers.

A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions

Tsutomu Sasao, Yukihiro Iguchi, Yuta Urano, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

Implementation of multiple-output functions using PQMDDs

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

A Random Forest Using a Multi-valued Decision Diagram on an FPGA

Tsutomu Sasao, Hiroki Nakahara, Akira Jinguji, 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, IEICE Trans. Inf. Syst..

Implementation of Multiple-Valued CAM Functions by LUT Cascades

Tsutomu Sasao, Jon T. Butler, 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions

Tsutomu Sasao, Tsutomu Sasao, 1991, IEEE Trans. Computers.

A design method for look-up table type FPGA by pseudo-Kronecker expansion

Tsutomu Sasao, Jon T. Butler, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

A deep convolutional neural network based on nested residue number system

Tsutomu Sasao, Hiroki Nakahara, Tsutomu Sasao, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Implementations of Reconfigurable Logic Arrays on FPGAs

Tsutomu Sasao, Hiroki Nakahara, 2007, 2007 International Conference on Field-Programmable Technology.

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2016, J. Multiple Valued Log. Soft Comput..

A method to evaluate logic functions in the presence of unknown inputs using LUT cascades

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

On the Complexity of Classification Functions

Tsutomu Sasao, 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

Input Variable Assignment and Output Phase Optimization of PLA's

Tsutomu Sasao, Tsutomu Sasao, 1984, IEEE Transactions on Computers.

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix

Tsutomu Sasao, Yukihiro Iguchi, Yuta Urano, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Ternary decision diagrams. Survey

Tsutomu Sasao, Tsutomu Sasao, 1997, Proceedings 1997 27th International Symposium on Multiple- Valued Logic.

Shared multiple-valued decision diagrams for multiple-output functions

Tsutomu Sasao, Hafiz Md. Hasan Babu, 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

Combinatorial Computing-One Object Per Clock

Tsutomu Sasao, Jon T. Butler, 2013 .

On the Complexity of Error Detection Functions for Redundant Residue Number Systems

Tsutomu Sasao, Yukihiro Iguchi, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Cascade realization 3-input 3-output conservative logic circuits — application of three-valued logic to two-valued logic —

Kozo Kinoshita, Tsutomu Sasao, 1976 .

An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

Efficient computation of canonical form for boolean matching in large libraries

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Hardware Index to Set Partition Converter

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2013, ARC.

Linear decomposition of index generation functions

Tsutomu Sasao, 2012, 17th Asia and South Pacific Design Automation Conference.

Realization of Minimum Circuits with Two-Input Conservative Logic Elements

Kozo Kinoshita, Tsutomu Sasao, 1978, IEEE Transactions on Computers.

A fast logic simulator using a look up table cascade emulator

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2006, Asia and South Pacific Conference on Design Automation, 2006..

On a Memory-Based Realization of Sparse Multiple-Valued Functions

Tsutomu Sasao, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).

EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions

Tsutomu Sasao, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams

Tsutomu Sasao, Tsutomu Sasao, 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

Totally undecomposable functions: applications to efficient multiple-valued decompositions

Tsutomu Sasao, 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

The Parallel Sieve Method for a Virus Scanning Engine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Spectral Transform Decision Diagrams

Claudio Moraga, Radomir S. Stankovic, Tsutomu Sasao, 1996 .

Applications of Zero-Suppressed Decision Diagrams

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2014, Applications of Zero-Suppressed Decision Diagrams.

On the average path length in decision diagrams of multiple-valued functions

Tsutomu Sasao, Jon T. Butler, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

Implementation of LPM Address Generators on FPGAs

Tsutomu Sasao, Jon T. Butler, Hui Qin, 2006, ARC.

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multiple-valued combinational circuits with feedback

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

Realization of regular ternary logic functions using double-rail logic

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Three parameters to find functional decompositions

Tsutomu Sasao, Ken-ichi Kurimoto, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Development of Self-Localization System in the Mountain Forest for Field Robot

Tsutomu Sasao, Eiji Hayashi, Ayumu Tominaga, 2017 .

On the number of dependent variables for incompletely specified multiple-valued functions

Tsutomu Sasao, 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

Soft-error tolerant TCAMs for high-reliability packet classifications

Tsutomu Sasao, Infall Syafalni, Xiaoqing Wen, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, IEICE Trans. Inf. Syst..

A Design Algorithm for Sequential Circuits Using LUT Rings

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic

Tsutomu Sasao, 2001, Proceedings 31st IEEE International Symposium on Multiple-Valued Logic.

A CAM Emulator Using Look-Up Table Cascades

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

A TCAM generator for packet classification

Tsutomu Sasao, Infall Syafalni, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Index Generation Functions: Minimization Methods

Tsutomu Sasao, 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

Representations of Elementary Functions Using Edge-Valued MDDs

Shinobu Nagayama, Tsutomu Sasao, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

2011 41st IEEE International Symposium on Multiple-Valued Logic

Tsutomu Sasao, 2011 .

On the number of segments needed in a piecewise linear approximation

Tsutomu Sasao, Jon T. Butler, C. L. Frenzen, 2010, J. Comput. Appl. Math..

Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple-valued decision diagrams

Tsutomu Sasao, Hafiz Md. Hasan Babu, 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).

DECOMPOS : An integrated system for functional decomposition

Tsutomu Sasao, Tsutomu Sasao, 1998 .

EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions

Tsutomu Sasao, 1990, Proceedings of the Twentieth International Symposium on Multiple-Valued Logic.

On the minimization of SOPs for bi-decomposition functions

Tsutomu Sasao, Jon T. Butler, 2001, ASP-DAC '01.

Minimization of AND-EXOR Expressions Using Rewrite Rules

Tsutomu Sasao, Daniel Brand, D. Brand, 1993, IEEE Trans. Computers.

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD

Tsutomu Sasao, Hiroki Nakahara, Hiroyuki Nakanishi, 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

High-Speed Hardware Partition Generation

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2015, TRETS.

A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Index to Constant Weight Codeword Converter

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2011, ARC.

BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition

Tsutomu Sasao, Munehiro Matsuura, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Fast Boolean matching under permutation using representative

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

On the Number of Fanout-Free Functions and Unate Cascade Functions

Kozo Kinoshita, Tsutomu Sasao, 1979, IEEE Transactions on Computers.

Representation of Incompletely Specified Switching Functions Using Pseudo-Kronecker Decision Diagrams

Tsutomu Sasao, Munehiro Matsuura, 2001 .

An Implementation of an Address Generator Using Hash Memories

Tsutomu Sasao, Munehiro Matsuura, Tsutomu Sasao, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Row-shift decompositions for index generation functions

Tsutomu Sasao, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, IEICE Trans. Inf. Syst..

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

A soft-error tolerant TCAM using partial don't-care keys

Tsutomu Sasao, Infall Syafalni, Xiaoqing Wen, 2015, 2015 20th IEEE European Test Symposium (ETS).

Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs

Tsutomu Sasao, Debatosh Debnath, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Hardware Index to Permutation Converter

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

A hardware simulation engine based on decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A CAM Emulator UsingLook-UpTableCascades

Tsutomu Sasao, Hiroki Nakahara, 2007 .

A Comparison of Architectures for Various Decision Diagram Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

Fault Diagnosis for RAMs Using Walsh Spectrum

Tsutomu Sasao, Yukihiro Iguchi, Atsumu Iseno, 2004, IEICE Trans. Inf. Syst..

Encoding of Boolean Functions and its Application to LUT Cascade Synthesis

Tsutomu Sasao, Alan Mishchenko, A. Mishchenko, 2002, IWLS.

On the adders with minimum tests

Tsutomu Sasao, Seiji Kajihara, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An algorithm to find optimum support-reducing decompositions for index generation functions

Tsutomu Sasao, Yukihiro Iguchi, Kyu Matsuura, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method

Tsutomu Sasao, 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

Comparison of Decision Diagrams for Multiple-Output Logic Functions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2002, IWLS.

Linear Decompositions for Multi-Valued Input Classification Functions

Tsutomu Sasao, Jon T. Butler, 2021, 2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL).

Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2021, 2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL).

A Design Method for Multiclass Classifiers

Tsutomu Sasao, Yukihiro Iguchi, Yuto Horikawa, 2021, 2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL).

Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm (Special Section on VLSI Design and CAD Algorithms)

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 1996 .

PAPER Special Section on VLSI Design and CAD Algorithms Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 2004 .

Input VariableAssignment andOutput PhaseOptimization ofPLA's

Tsutomu Sasao, 1984 .

LUTMIN : FPGA Logic Synthesis with MUX-Based and Cascade Realizations

Tsutomu Sasao, Alan Mishchenko, 2009 .

Exact Minimization of FPRMs Using Multi-Terminal Exor TDDs

Tsutomu Sasao, Fumitaka Izuhara, Tsutomu Sasao, 1996 .

Analysis of the Number of Variables to Represent Index Generation Functions

Tsutomu Sasao, Jon T. Butler, 2017 .

Exact Minimization of AND - EXOR Expressions using Multi - terminal EXOR Ternary Decision Diagrams.

Tsutomu Sasao, Fumitaka Izuhara, 1995 .

Application of LUT cascades to numerical function generators

Tsutomu Sasao, Jon T. Butler, Marc D. Riedel, 2004 .

Reduction of the Number of Variables

Tsutomu Sasao, 2011 .

Or-and-Or Three-Level Networks

Tsutomu Sasao, Tsutomu Sasao, 1996 .

Compact BDD Representations for Multiple-Output Functions and Their Application

Shinobu Nagayama, Tsutomu Sasao, 2001 .

Average number of nodes in binary decision diagrams of Fibonacci func tions

Tsutomu Sasao, Jon T. Butler, 1996 .

LUT cascades and emulators for realizations of logic functions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2005 .

On Bi-Decompositions of Logic Functions

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 1997 .

Application of multiple-valued logic to a serial decomposition of PLAs

Tsutomu Sasao, 1989, Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic.

Area-Time Complexities of Multi-Valued Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, 2004 .

Heuristics to Minimize Multiple-Valued Decision Diagrams

Tsutomu Sasao, Hafiz Md. Hasan Babu, 2000 .

An exact minimization algorithm for generalized Reed-Muller expressions

Tsutomu Sasao, D. Dednath, 1994, Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.

Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2002 .

LP Characteristic Vector for Logic Functions

Tsutomu Sasao, Tsutomu Sasao, N. Koda, 1993 .

An Efficient Heuristic Algorithm for Linear Decomposition of Index Generation Functions

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2015 .

On the numbers of variables to represent sparse logic functions

Tsutomu Sasao, 2008, ICCAD 2008.

Easily testable realizations for generalized Reed-Muller expressions

Tsutomu Sasao, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Ternary Decision Diagrams and their Applications

Tsutomu Sasao, Tsutomu Sasao, 1996 .

A Realization of Index Generation Functions Using Modules of Uniform Sizes

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010 .

Three parameters to find functional decompositions

Tsutomu Sasao, Ken-ichi Kurimoto, 2000, ASP-DAC '00.

The Eigenfunction of the Reed-Muller transformation

Tsutomu Sasao, Jon T. Butler, 2007 .

Distance Duality on Some Classes of Boolean Functions

Tsutomu Sasao, Jon T. Butler, Pantelimon Stănică, 2016 .

Logic functions for cryptography - A tutorial

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 2009 .

Representations of Logic Functions Using EXOR Operators

Tsutomu Sasao, Tsutomu Sasao, 1996 .

On the Complexity of Three-Level Logic Circuits(Complexity Theory and Related Topics)

Tsutomu Sasao, Tsutomu Sasao, 1990 .

A New Expansion of Symmetric Functions and Their Application to Non-Disjoint Functional Decompositions for LUT Type FPGAs

Tsutomu Sasao, Tsutomu Sasao, 2000 .

Minimization of average path length in BDDs by variable reordering

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, 2003 .

An application of multiple-valued logic to a design of programmable logic arrays

Tsutomu Sasao, 1978, MVL '78.

Efficient computation of canonical form for Boolean matching in large libraries

Tsutomu Sasao, Debatosh Debnath, Tsutomu Sasao, 2004 .

Planar Decision Diagrams for Multiple-Valued Functions

Tsutomu Sasao, Jon T. Butler, J. T. Butler, 1996 .