Munehiro Matsuura

发表

Representations of logic functions using QRMDDs

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

A regular expression matching using non-deterministic finite automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroshi Nakahara, 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, ISMVL.

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables

Tsutomu Sasao, Munehiro Matsuura, Takaaki Nakamura, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A Quaternary Decision Diagram Machine and the Optimization of its Code

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2009, 2009 39th International Symposium on Multiple-Valued Logic.

Realization of Regular Ternary Logic Functions.

Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, 1999 .

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2015, IEICE Trans. Inf. Syst..

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

An Implementation of an Address Generator Using Hash Memories

Munehiro Matsuura, Tsutomu Sasao, 2007 .

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, J. Multiple Valued Log. Soft Comput..

A Design Method for Irredundant Cascades

Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, 2002 .

A Regular Expression Matching Circuit Based on a Decomposed Automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2011, ARC.

An Architecture for IPv6 Lookup Using Parallel Index Generation Units

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, ARC.

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, J. Multiple Valued Log. Soft Comput..

A hardware simulation engine based on decision diagrams (short paper)

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, ASP-DAC '00.

A Quaternary Decision Diagram Machine: Optimization of Its Code

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2010, IEICE Trans. Inf. Syst..

A virus scanning engine using a parallel finite-input memory machine and MPUs

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A Packet Classifier Using Parallel EVMDD (k) Machine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 IEEE 7th International Symposium on Embedded Multicore Socs.

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, J. Multiple Valued Log. Soft Comput..

On a prefetching heterogeneous MDD machine

Munehiro Matsuura, Tsutomu Sasao, Hiroki Nakahara, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic.

A method to decompose multiple-output logic functions

Munehiro Matsuura, Tsutomu Sasao, 2004, Proceedings. 41st Design Automation Conference, 2004..

A Method to Realize Logic Functions using LUTs and OR Gates

Tsutomu Sasao, Munehiro Matsuura, Tsutomu Sasao, 2003 .

Design Methods of Radix Converters Using Arithmetic Decompositions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2007, IEICE Trans. Inf. Syst..

On a Decomposed MTMDDs for CF Machine

Munehiro Matsuura, Tsutomu Sasao, Hiroki Nakahara, 2012 .

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, Microprocess. Microsystems.

A Packet Classifier Using a Parallel Branching Program Machine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Average path length of binary decision diagrams

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2005, IEEE Transactions on Computers.

On properties of Kleene TDDs

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Realization of multiple-output functions by reconfigurable cascades

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

A Parallel Branching Program Machine for Emulation of Sequential Circuits

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, ARC.

Multi-level Logic Synthesis Based on Pseudo-Kronecker Decision Diagrams and Local Transformation

Munehiro Matsuura, Tsutomu Sasao, H. Hamachi, 1995 .

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

An evaluation system for logic functions based on decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2004 .

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2006 .

On a Method to Reduce the Number of LUTs in LUT cascades

Munehiro Matsuura, Tsutomu Sasao, Hayato Gouji, 2001 .

A Realization of Cycle-based Simulation Engine using Decision Diagrams

Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, 1999 .

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades

Tsutomu Sasao, Munehiro Matsuura, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Bi-Partition of Shared Binary Decision Diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2002 .

A Packet Classifier Based on Prefetching EVMDD (k) Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, IEICE Trans. Inf. Syst..

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, ARC.

Evaluation of multiple-output logic functions using decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2003, ASP-DAC '03.

A packet classifier using LUT cascades based on EVMDDS (k)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

A Design Algorithm for Sequential Circuit Synthesis using LUT Ring

Munehiro Matsuura, Tsutomu Sasao, Hiroki Nakahara, 2004 .

Implementation of multiple-output functions using PQMDDs

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2013, IEICE Trans. Inf. Syst..

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2016, J. Multiple Valued Log. Soft Comput..

A method to evaluate logic functions in the presence of unknown inputs using LUT cascades

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

A fast logic simulator using a look up table cascade emulator

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2006, Asia and South Pacific Conference on Design Automation, 2006..

The Parallel Sieve Method for a Virus Scanning Engine

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Realization of regular ternary logic functions using double-rail logic

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2012, IEICE Trans. Inf. Syst..

A Design Algorithm for Sequential Circuits Using LUT Rings

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A CAM Emulator Using Look-Up Table Cascades

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

FPGA Design using Pseudo-Kronecker Decision Diagrams

Munehiro Matsuura, Tsutomu Sasao, Ken-ichi Kurimoto, 2000 .

BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition

Tsutomu Sasao, Munehiro Matsuura, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Representation of Incompletely Specified Switching Functions Using Pseudo-Kronecker Decision Diagrams

Tsutomu Sasao, Munehiro Matsuura, 2001 .

An Implementation of an Address Generator Using Hash Memories

Tsutomu Sasao, Munehiro Matsuura, Tsutomu Sasao, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, IEICE Trans. Inf. Syst..

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

A hardware simulation engine based on decision diagrams

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A Comparison of Architectures for Various Decision Diagram Machines

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

Comparison of Decision Diagrams for Multiple-Output Logic Functions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2002, IWLS.

LUT cascades and emulators for realizations of logic functions

Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura, 2005 .

Area-Time Complexities of Multi-Valued Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, 2004 .

Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams

Tsutomu Sasao, Munehiro Matsuura, Jon T. Butler, 2002 .

A Realization of Index Generation Functions Using Modules of Uniform Sizes

Tsutomu Sasao, Munehiro Matsuura, Hiroki Nakahara, 2010 .