Sarma B. K. Vrudhula

发表

David Blaauw, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2003, ICCAD.

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, S. Vrudhula, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Extending the lifetime of fuel cell based hybrid systems

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Disk drive energy optimization for audio-video applications

Sarma B. K. Vrudhula, Musaravakkam S. Krishnan, Ravishankar Rao, 2004, CASES '04.

An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems

Sarma B. K. Vrudhula, Daler N. Rakhmatov, S. Vrudhula, 2001, ICCAD.

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Static power optimization of deep submicron CMOS circuits for dual VT technology

Sarma B. K. Vrudhula, Qi Wang, S. Vrudhula, 1998, ICCAD.

High-level power management of embedded systems with application-specific energy cost functions

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

Sarma B. K. Vrudhula, Janet Roveda, Praveen Ghanta, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors

Sarma B. K. Vrudhula, Ravishankar Rao, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, S. Vrudhula, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Throughput optimal task allocation under thermal constraints for multi-core processors

Sarma B. K. Vrudhula, Ravishankar Rao, Karam S. Chatha, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Probabilistic analysis of interconnect coupling noise

David Blaauw, Sarma B. K. Vrudhula, Supamas Sirichotiyakul, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Analytical results for design space exploration of multi-core processors employing thread migration

Sarma B. K. Vrudhula, Ravishankar Rao, Krzysztof S. Berezowski, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States

Sarma B. K. Vrudhula, Kaviraj Chopra, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Performance optimal speed control of multi-core processors under thermal constraints

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Variational delay metrics for interconnect timing analysis

David Blaauw, Sani R. Nassif, Sarma B. K. Vrudhula, 2004, Proceedings. 41st Design Automation Conference, 2004..

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2008, J. Low Power Electron..

Digital IP protection using threshold voltage control

Sarma B. K. Vrudhula, Joseph Davis, Niranjan Kulkarni, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Performance optimal processor throttling under thermal constraints

Sarma B. K. Vrudhula, Ravishankar Rao, 2007, CASES '07.

DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference

Carole-Jean Wu, Sarma B. K. Vrudhula, Akhil Arunkumar, 2018, 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

The Impact of NBTI on the Performance of Combinational and Sequential Circuits

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Multi-level logic optimization for low power using local logic transformations

Sarma B. K. Vrudhula, Qi Wang, 1996, Proceedings of International Conference on Computer Aided Design.

EPIMap: Using Epimorphism to map applications on CGRAs

Aviral Shrivastava, Sarma B. K. Vrudhula, Mahdi Hamzeh, 2012, DAC Design Automation Conference 2012.

Computation of Joint Timing Yield of Sequential Networks Considering Process Variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel, 2007, PATMOS.

Analysis of Power Supply Noise in the Presence of Process Variations

Sarma B. K. Vrudhula, Praveen Ghanta, 2007, IEEE Design & Test of Computers.

Battery optimization vs energy optimization: which to choose and when?

Sarma B. K. Vrudhula, Ravishankar Rao, S. Vrudhula, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices

Sarma B. K. Vrudhula, Krzysztof S. Berezowski, S. Vrudhula, 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

Statistical waveform and current source based standard cell models for accurate timing analysis

Sarma B. K. Vrudhula, Amit Goel, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Analysis of discharge techniques for multiple battery systems

Sarma B. K. Vrudhula, Ravishankar Rao, Daler N. Rakhmatov, 2003, ISLPED '03.

Enabling Multithreading on CGRAs

Aviral Shrivastava, Sarma B. K. Vrudhula, Reiley Jeyapaul, 2011, 2011 International Conference on Parallel Processing.

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning

Shimeng Yu, Yu Cao, Jieping Ye, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

Battery lifetime prediction for energy-aware computing

Sarma B. K. Vrudhula, Daler N. Rakhmatov, Deborah A. Wallach, 2002, ISLPED '02.

Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture

Sarma B. K. Vrudhula, Niranjan Kulkarni, Nishant Nukala, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Estimation of signal arrival times in the presence of delay noise

David Blaauw, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2002, ICCAD 2002.

An investigation of power delay trade-offs for dual V/sub t/ CMOS circuits

Sarma B. K. Vrudhula, Qi Wang, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Variational interconnect delay metrics for statistical timing analysis

Sarma B. K. Vrudhula, Praveen Ghanta, S. Vrudhula, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates

Sarma B. K. Vrudhula, Joseph Davis, Jae-sun Seo, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors

Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Estimation of the likelihood of capacitive coupling noise

David Blaauw, Sarma B. K. Vrudhula, Supamas Sirichotiyakul, 2002, DAC '02.

Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks

Sarma B. K. Vrudhula, Marwan Krunz, Vinay Hanumaiah, 2014, ACM Trans. Sens. Networks.

A framework for battery-aware sensor management

Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Behavioral synthesis of field programmable analog array circuits

Haibo Wang, Sarma B. K. Vrudhula, S. Vrudhula, 2002, TODE.

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, S. Vrudhula, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Statistical library characterization using arbitrary polynomial chaos

Sarma B. K. Vrudhula, Sule Ozev, Mehmet Ince, 2017, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS).

Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks pdf

Sarma B. K. Vrudhula, Niranjan Kulkarni, 2016, ArXiv.

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

Sarma B. K. Vrudhula, Krzysztof S. Berezowski, Xiaoyin Yao, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Computation and refinement of statistical bounds on circuit delay

David Blaauw, Sarma B. K. Vrudhula, Vladimir Zolotov, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2018, Integr..

Analysis of signal probability in logic circuits using stochastic models

Sarma B. K. Vrudhula, Amitava Majumdar, S. Vrudhula, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Branch-aware loop mapping on CGRAs

Aviral Shrivastava, Sarma B. K. Vrudhula, Mahdi Hamzeh, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

A clock skewing strategy to reduce power and area of ASIC circuits

Sarma B. K. Vrudhula, Niranjan Kulkarni, Aykut Dengi, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

FGILP: an integer linear program solver based on function graphs

Sarma B. K. Vrudhula, Massoud Pedram, Yung-Te Lai, 1993, ICCAD.

Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila

Sarma B. K. Vrudhula, Seungchan Kim, Tejaswi Gowda, 2008, BIODEVICES.

Reliability-aware thermal management for hard real-time applications on multi-core processors

Sarma B. K. Vrudhula, Vinay Hanumaiah, 2011, 2011 Design, Automation & Test in Europe.

STEAM: A Smart Temperature and Energy Aware Multicore Controller

Carole-Jean Wu, Sarma B. K. Vrudhula, Vinay Hanumaiah, 2014, TECS.

Data driven power optimization of sequential circuits

Sarma B. K. Vrudhula, Qi Wang, 1998, Proceedings Design, Automation and Test in Europe.

Throughput of multi-core processors under thermal constraints

Chaitali Chakrabarti, Sarma B. K. Vrudhula, Ravishankar Rao, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

On short circuit power estimation of CMOS inverters

Sarma B. K. Vrudhula, Qi Wang, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Stochastic power grid analysis considering process variations

Rajendran Panda, Sarma B. K. Vrudhula, Janet Roveda, 2005, Design, Automation and Test in Europe.

Temperature dependent wire delay estimation in floorplanning

Wei Liu, Sarma B. K. Vrudhula, Alberto Nannarelli, 2011, 2011 NORCHIP.

A design of a fast and area efficient multi-input Muller C-element

Sarma B. K. Vrudhula, T.-Y. Wuu, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Stochastic analysis of interconnect performance in the presence of process variations

Sarma B. K. Vrudhula, Janet Roveda, Praveen Ghanta, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Time-to-failure estimation for batteries in portable electronic systems

Sarma B. K. Vrudhula, Daler N. Rakhmatov, 2001, ISLPED '01.

Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture

Sarma B. K. Vrudhula, Niranjan Kulkarni, Nishant Nukala, 2014, J. Parallel Distributed Comput..

A Technique for Estimating Signal Activity in Logic Circuits

Sarma B. K. Vrudhula, Hong-Yu Xie, 1998, Integr. Comput. Aided Eng..

LOTUS: leakage optimization under timing uncertainty for standard-cell designs

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Shimeng Yu, Sarma B. K. Vrudhula, Niranjan Kulkarni, 2014, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons

Sarma B. K. Vrudhula, W. Chen, Michael N. Kozicki, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Power balanced coverage-time optimization for clustered wireless sensor networks

Sarma B. K. Vrudhula, Marwan Krunz, Tao Shu, 2005, MobiHoc '05.

Stochastic variational analysis of large power grids considering intra-die correlations

Rajendran Panda, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Energy profiler for hardware/software co-design

Sarma B. K. Vrudhula, Raghukiran Sreeramaneni, S. Vrudhula, 2004, 17th International Conference on VLSI Design. Proceedings..

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Energy-Optimal Speed Control of a Generic Device

Sarma B. K. Vrudhula, Ravishankar Rao, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells

Sarma B. K. Vrudhula, Michael N. Kozicki, Hugh J. Barnaby, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Temperature and Process Variations Aware Power Gating of Functional Units

Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Macro-instruction generation for dynamic logic caching

Sarma B. K. Vrudhula, K. McCarley, 1997, Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype.

High-performance face detection with CPU-FPGA acceleration

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Minimizing area and power of sequential CMOS circuits using threshold decomposition

Sarma B. K. Vrudhula, Niranjan Kulkarni, Nishant Nukala, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Framework for Statistical Timing Analysis using Non-Linear Delay and Slew Models

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Scalable model for predicting the effect of negative bias temperature instability for reliable design

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2008, IET Circuits Devices Syst..

Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts

Sarma B. K. Vrudhula, King C. Ho, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Probability distribution of signal arrival times using Bayesian networks

David Blaauw, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design

Haibo Wang, Sarma B. K. Vrudhula, Saravanan Ramamoorthy, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Statistical timing analysis using bounds [IC verification]

David Blaauw, Sarma B. K. Vrudhula, Vladimir Zolotov, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Thermal aware floorplanning incorporating temperature dependent wire delay estimation

Wei Liu, Sarma B. K. Vrudhula, Alberto Nannarelli, 2015, Microprocess. Microsystems.

Combinational equivalence checking for threshold logic circuits

Sarma B. K. Vrudhula, Goran Konjevod, Tejaswi Gowda, 2007, GLSVLSI '07.

A methodology to improve timing yield in the presence of process variations

Sarma B. K. Vrudhula, Janet Roveda, Sreeja Raj, 2004, Proceedings. 41st Design Automation Conference, 2004..

Battery Modeling for Energy-Aware System Design

Sarma B. K. Vrudhula, Ravishankar Rao, Daler N. Rakhmatov, 2003, Computer.

Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks

Sarma B. K. Vrudhula, Marwan Krunz, Tao Shu, 2006, IEEE Transactions on Wireless Communications.

Rapid prototyping of networks of asynchronous multiple functional units

Sarma B. K. Vrudhula, E. Tsun, S. Vrudhula, 1997, Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype.

Battery-conscious task sequencing for portable devices including voltage/clock scaling

Chaitali Chakrabarti, Sarma B. K. Vrudhula, Daler N. Rakhmatov, 2002, DAC '02.

Fault Coverage and Test Length Estimation for Random Pattern Testing

Sarma B. K. Vrudhula, Amitava Majumdar, 1995, IEEE Trans. Computers.

Estimation of signal arrival times in the presence of delay noise

David Blaauw, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Decomposition based approach for synthesis of multi-level threshold logic circuits

Sarma B. K. Vrudhula, Tejaswi Gowda, S. Vrudhula, 2008, 2008 Asia and South Pacific Design Automation Conference.

Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Shimeng Yu, Yu Cao, Jieping Ye, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity

Shimeng Yu, Yu Cao, Jieping Ye, 2014, BICA.

Predictive Modeling of the NBTI Effect for Reliable Design

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, IEEE Custom Integrated Circuits Conference 2006.

Energy optimal speed control of a producer--consumer device pair

Sarma B. K. Vrudhula, Ravishankar Rao, 2007, TECS.

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

Shimeng Yu, Yu Cao, Jieping Ye, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations

Sarma B. K. Vrudhula, Amit Goel, Praveen Ghanta, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints

Sarma B. K. Vrudhula, Ravishankar Rao, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis

Sarma B. K. Vrudhula, Massoud Pedram, Yung-Te Lai, 1993, 30th ACM/IEEE Design Automation Conference.

Energy optimal speed control of devices with discrete speed sets

Sarma B. K. Vrudhula, Ravishankar Rao, R. Rao, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee

Carole-Jean Wu, Sarma B. K. Vrudhula, Benjamin Gaudette, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Power Reduction of Functional Units Considering Temperature and Process Variations

Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Hardware-software bipartitioning for dynamically reconfigurable systems

Sarma B. K. Vrudhula, Daler N. Rakhmatov, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

Adaptive Multiuser Online Reconfigurable Engine

Sarma B. K. Vrudhula, Daler N. Rakhmatov, Thomas J. Brown, 2000, IEEE Des. Test Comput..

Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2009, IEEE Trans. Very Large Scale Integr. Syst..

Identification of Threshold Functions and Synthesis of Threshold Networks

Sarma B. K. Vrudhula, Krzysztof S. Berezowski, Tejaswi Gowda, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Sarma B. K. Vrudhula, Jae-sun Seo, Niranjan Kulkarni, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implicit pseudo boolean enumeration algorithms for input vector control

Sarma B. K. Vrudhula, Kaviraj Chopra, 2004, Proceedings. 41st Design Automation Conference, 2004..

Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic

Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Kaviraj Chopra, 2004, 17th International Conference on VLSI Design. Proceedings..

An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing

Sarma B. K. Vrudhula, Aykut Dengi, Elham Azari, 2019, FPGA.

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2006, J. Low Power Electron..

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Yu Cao, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits

Sarma B. K. Vrudhula, Qi Wang, S. Vrudhula, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling

Sarma B. K. Vrudhula, Vinay Hanumaiah, S. Vrudhula, 2014, IEEE Transactions on Computers.

Power reduction and power-delay trade-offs using logic transformations

Sarma B. K. Vrudhula, Qi Wang, Shantanu Ganguly, 1999, TODE.

Optimal range assignment in solar powered active wireless sensor networks

Sarma B. K. Vrudhula, Marwan Krunz, Vinay Hanumaiah, 2012, 2012 Proceedings IEEE INFOCOM.

An Optimal Analytical Solution for Processor Speed Control with Thermal Constraints

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Automatic design of binary and multiple-valued logic gates on RTD series

Sarma B. K. Vrudhula, Krzysztof S. Berezowski, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

End-to-end scalable FPGA accelerator for deep residual networks

Yu Cao, Sarma B. K. Vrudhula, Minkyu Kim, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Techniques for estimating test length under random test

Sarma B. K. Vrudhula, Amitava Majumdar, 1994, J. Electron. Test..

REGIMap: Register-aware application mapping on Coarse-Grained Reconfigurable Architectures (CGRAs)

Aviral Shrivastava, Sarma B. K. Vrudhula, Mahdi Hamzeh, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Design of threshold logic gates using emerging devices

Sarma B. K. Vrudhula, Jinghua Yang, Niranjan Kulkami, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy management for battery-powered embedded systems

Sarma B. K. Vrudhula, Daler N. Rakhmatov, S. Vrudhula, 2003, TECS.

Current source based standard cell model for accurate signal integrity and timing analysis

Sarma B. K. Vrudhula, Amit Goel, 2008, 2008 Design, Automation and Test in Europe.

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo, 2017, FPGA.

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A scalable parallel H.264 decoder on the cell broadband engine architecture

Sarma B. K. Vrudhula, Karam S. Chatha, Michael A. Baker, 2009, CODES+ISSS '09.

A fuel-cell-battery hybrid for portable embedded systems

Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula, 2008, TODE.

Energy optimization for a two-device data flow chain

Sarma B. K. Vrudhula, Ravishankar Rao, R. Rao, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

Shimeng Yu, Yu Cao, Jieping Ye, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Minimizing routing configuration cost in dynamically reconfigurable FPGAs

Sarma B. K. Vrudhula, Daler N. Rakhmatov, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation

Sarma B. K. Vrudhula, Vinay Hanumaiah, Gayathri Chalivendra, 2011, GLSVLSI '11.

The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits

Yu Cao, Sarma B. K. Vrudhula, Matteo Cavaliere, 2014, Fundam. Informaticae.

Formal Verification Using Edge-Valued Binary Decision Diagrams

Sarma B. K. Vrudhula, Massoud Pedram, Yung-Te Lai, 1996, IEEE Trans. Computers.

Statistical timing analysis using bounds and selective enumeration

David Blaauw, Sarma B. K. Vrudhula, Vladimir Zolotov, 2003, TAU '02.

Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors

Sarma B. K. Vrudhula, Vinay Hanumaiah, S. Vrudhula, 2012, IEEE Transactions on Computers.

FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area

Sarma B. K. Vrudhula, Jinghua Yang, Aykut Dengi, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Energy-Efficient Mapping for a Network of DNN Models at the Edge

Carole-Jean Wu, Sarma B. K. Vrudhula, Soroush Heidari, 2021, 2021 IEEE International Conference on Smart Computing (SMARTCOMP).

An investigation of power delay trade-offs on PowerPC circuits

Sarma B. K. Vrudhula, Qi Wang, Shantanu Ganguly, 1997, DAC.

FGILP: an integer linear program solver based on function graphs

Sarma B. K. Vrudhula, Massoud Pedram, Yung-Te Lai, 1993, ICCAD '93.

DYNAMICALLY RECONFIGURABLE ANALOG / DIGITAL HARDWARE-IMPLEMENTATION USING FPGA AND FPAA TECHNOLOGIES

Sarma B. K. Vrudhula, Daler Rakhmatov, Olgierd A. Palusinski, 1999 .