Qianjian Xing

Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern

Feng Yu, Xiaobo Yin, Bei Zhao, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture

Feng Yu, Qianjian Xing, Zhen-guo Ma, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Fused Continuous Floating-Point MAC on FPGA

Feng Yu, Qianjian Xing, Min Yuan, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy

Feng Yu, Tingting Chen, Weijun Li, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Pipelined Architecture for a Radix-2 Fast Walsh–Hadamard–Fourier Transform Algorithm

Feng Yu, Xiaobo Yin, Qianjian Xing, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.