Alexis Farcy

发表

First integration of Cu TSV using die-to-wafer direct bonding and planarization

Léa Di Cioccio, Thomas Signamarcheix, Laurent Bally, 2009, 2009 IEEE International Conference on 3D System Integration.

RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits

Thierry Lacrevaz, Patrick Leduc, Alexis Farcy, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

Pascal Ancey, Alexandre Valentian, Patrick Leduc, 2009, 2009 IEEE International Conference on 3D System Integration.

Through Silicon Capacitors (TSC) for noise reduction in Power Distribution Network

Yann Lamy, Thierry Lacrevaz, Bernard Flechet, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Editorial: MAM 2012 (selected contributions) March 11-14, Grenoble, France Minatec Campus

Sylvain Maitrejean, Alexis Farcy, Thierry Chevolleau, 2013 .

Dielectric LossEffects ontheModeling ofInterconnect Responses forthe45nmNode

Thierry Lacrevaz, Cedric Bermond, Bernard Flechet, 2008 .

Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking

Thierry Lacrevaz, Pascal Ancey, Christian Gontrand, 2009, 2009 IEEE International Conference on 3D System Integration.

EUROSERVER: Energy Efficient Node for European Micro-Servers

Paul M. Carpenter, Iakovos Mavroidis, Angelos Bilas, 2014, 2014 17th Euromicro Conference on Digital System Design.

Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability

Stéphane Moreau, F. Fournel, Didier Lattard, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters

Christian Bernard, Fabien Clermidy, Alain Greiner, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Wide-band simulations of differential 3D interconnect propagation performances in a photonic interposer

Thierry Lacrevaz, Bernard Flechet, Alexis Farcy, 2016, 2016 6th Electronic System-Integration Technology Conference (ESTC).

Performance predictions of interconnect networks for advanced technology nodes

Cedric Bermond, Bernard Flechet, Pascal Ancey, 2009 .

Impact of dummies on interconnects network HF propagation performances for the 65nm node

Cedric Bermond, Bernard Flechet, B. Blampey, 2006 .

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

Jean Michel Portal, Frédéric Boeuf, Alexis Farcy, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Impact of process parameters on circuit performance for the 32nm technology node

Cedric Bermond, Bernard Flechet, B. Blampey, 2007 .

Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer

Thierry Lacrevaz, Alexis Farcy, Cédric Bermond, 2014, 2014 International 3D Systems Integration Conference (3DIC).

3D interconnect optimization for single channel 100-GBps transmission in a photonic interposer

Thierry Lacrevaz, Alexis Farcy, Philippe Artillan, 2017, 2017 IEEE 21st Workshop on Signal and Power Integrity (SPI).

Heat spreading packaging solutions for hybrid bonded 3D-ICs

Alexis Farcy, Séverine Cheramy, Jean-Philippe Colonna, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

Christian Bernard, Fabien Clermidy, Alain Greiner, 2021, IEEE Journal of Solid-State Circuits.

ITAC: A complete 3D integration test platform

Karim Azizi-Mourier, Stéphane Moreau, Gaël Pillonnet, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Electrical Model of Different Architectures of through Silicon Capacitors for High Frequency Power Distribution Network (PDN) Decoupling Operations

Yann Lamy, Thierry Lacrevaz, Alexis Farcy, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

Ricardo Reis, Pascal Vivet, François de Crecy, 2014, 2014 International 3D Systems Integration Conference (3DIC).

Integrated circuit comprising an auxiliary component such as a passive component or an MEMS, has above a microchip and method for making corresponding

Alexis Farcy, Philippe Coronel, Pascal Ancey, 2001 .

Influence of 3D integration on 2D interconnections and 2D self inductors HF properties

Thierry Lacrevaz, Lionel Cadix, Alexis Farcy, 2009, 2009 IEEE International Conference on 3D System Integration.

Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology

G. Cibrario, Patrick Leduc, Maxime Rousseau, 2008 .

Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix

Alexis Farcy, Melanie Brocard, Patrick Le Maitre, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

Frederic Boeuf, Alexis Farcy, B. Borot, 2008, ISQED 2008.

3D integration demonstration of a wireless product with design partitioning

Pascal Ancey, Laurent-Luc Chapelon, F. Leverd, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Thermal correlation between measurements and FEM simulations in 3D ICs

François de Crecy, M. Haykel Ben Jamaa, Alexis Farcy, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Electronic integrated circuit incorporating a capacitor

Alexis Farcy, Joaquim Torres, 2005 .

Impact of copper dummies on interconnect propagation performance in advanced integrated circuits

Cedric Bermond, Bernard Flechet, B. Blampey, 2004 .

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

Bernard Flechet, Myriam Assous, Maxime Rousseau, 2010 .

New techniques to characterize properties of advanced dielectric barriers for sub-65nm technology node

Laurent-Luc Chapelon, S. Jullian, Alexis Farcy, 2006 .

In situ microwave characterisation of medium-k hfo 2 and high-k srtio 3 dielectrics for metal-insulator-metal capacitors integrated in back-end of line of integrated circuits

Thierry Lacrevaz, Bernard Flechet, Y. Morand, 2008 .

Advanced Cu interconnects using air gaps

J. Michelon, Alexis Farcy, Roel Daamen, 2005 .

Performances of Wafer-Level UnderFill with 50µm pitch interconnections: Comparison with conventional underfill

Alexis Farcy, Nicolas Sillon, Sandrine Lhostis, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

Characterization and optimization of a new Cu/SiN/TaN/Cu damascene architecture for metal-insulator-metal capacitors

Thierry Lacrevaz, Bernard Flechet, Alexis Farcy, 2005 .

Integration of a high density Ta2O5 MIM capacitor following 3D damascene architecture compatible with copper interconnects

Alexis Farcy, Sebastien Cremer, E. Deloffre, 2006 .

Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking

Bernard Flechet, Alexandre Valentian, Maxime Rousseau, 2010 .

Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology

Patrick Leduc, Maxime Rousseau, Alexis Farcy, 2009, 2009 European Microelectronics and Packaging Conference.

RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits

Thierry Lacrevaz, Bernard Flechet, Alexis Farcy, 2014 .

MIM HfO/sub 2/ low leakage capacitors for eDRAM integration at interconnect levels

Yves Morand, Gilles Reimbold, Serge Blonkowski, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).