Inoue

A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs

Yamazaki, Kawamura, Shimizu, 1997, 1997 Symposium on VLSI Technology.

Development Of A New Television Set With Personal Computer Capability

Kobayashi, Inoue, Miyahara, 1997, 1997 International Conference on Consumer Electronics.

Gate Electrode Engineering By Control Of Grain Growth For High Performance And High Reliable 0.18/spl mu/m Dual Gate CMOS

Furukawa, Shimizu, Inoue, 1997, 1997 Symposium on VLSI Technology.

NACSIS. Decennial and the future.

Inoue, 1996 .

DEVELOPMENT OF DYNAMIC SIMULATOR FOR MARINE RISER SYSTEM:MARS93

Inoue, K-i, Y Kitakouji, 1994 .

An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

Li, Jiang, Minglu, 2008 .

A Programmable Video Codec System Low-bit-rate Communication

Okamoto, Fujimoto, Inoue, 1997, 1997 International Conference on Consumer Electronics.