Shui-Ming Cheng

High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Wei Jin, Jia Chen, C. Wann, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Scalability and biasing strategy for CMOS with active well bias

Bomy Chen, R. Dennard, Chih-Yung Lin, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

A 65nm node strained SOI technology with slim spacer

Chenming Hu, Tsai-Sheng Gau, Yee-Chia Yeo, 2003, IEEE International Electron Devices Meeting 2003.

A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles

Steve S. Chung, Mong-Song Liang, Shui-Ming Cheng, 1999 .

45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell

Chenming Hu, Mong-Song Liang, Di-Hong Lee, 2004 .

A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage

Steve S. Chung, Shui-Ming Cheng, Cherng-Ming Yih, 1998 .

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

Chenming Hu, Tsai-Sheng Gau, Jaw-Jung Shin, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..