Trong-Thuc Hoang

发表

Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter

Takahiro Hosaka, Trong-Thuc Hoang, Van-Phuc Hoang, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2018, 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

A low-resource low-latency hybrid adaptive CORDIC in 180-nm CMOS technology

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2015, TENCON 2015 - 2015 IEEE Region 10 Conference.

A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB pdf

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2019, Microprocess. Microsystems.

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors

Trong-Thuc Hoang, Cong-Kha Pham, Ckristian Duran, 2020, ISCAS.

A Real-time Image Feature Extraction Using Pulse-Coupled Neural Network

Trong-Thuc Hoang, Xuan-Thuan Nguyen, Trong-Tu Bui, 2012 .

Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2015, IEICE Electron. Express.

A parallel pipeline CORDIC based on adaptive angle selection

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2016, 2016 International Conference on Electronics, Information, and Communications (ICEIC).

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Low-resource low-latency hybrid adaptive CORDIC with floating-point precision

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2015, IEICE Electron. Express.

High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2019, 2019 IEEE International Conference on Industrial Technology (ICIT).

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2019, IEICE Electron. Express.

A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS

Trong-Thuc Hoang, Van-Phuc Hoang, Katsumi Inoue, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

A constraint-based watermarking technique using Schmitt Trigger insertion at logic synthesis level

Trong-Thuc Hoang, Trong-Tu Bui, Thai-Bao Huynh, 2013, 2013 International Conference on Advanced Technologies for Communications (ATC 2013).

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2020, IEICE Electron. Express.

An FSM-based IP protection technique using added watermarked states

Trong-Thuc Hoang, Trong-Tu Bui, Kim-Hung Nguyen, 2013, 2013 International Conference on Advanced Technologies for Communications (ATC 2013).

A CORDIC-based QR decomposition for MIMO signal detector

Trong-Thuc Hoang, Cong-Kha Pham, Xuan-Thuan Nguyen, 2018, IEICE Electron. Express.

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2020, Microprocess. Microsystems.

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2018, IEICE Electron. Express.

A floating-point FFT Twiddle factor implementation based on adaptive angle recoding CORDIC

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2017, 2017 International Conference on Recent Advances in Signal Processing, Telecommunications & Computing (SigTelCom).

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation

Trong-Thuc Hoang, Cong-Kha Pham, Xuan-Thuan Nguyen, 2018, IEEE Access.

A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications

Trong-Thuc Hoang, Anh-Vu Dinh-Duc, Trong-Tu Bui, 2014, 2014 International Conference on Advanced Technologies for Communications (ATC 2014).

FPGA-based frequent items counting using matrix of equality comparators

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

An efficient FPGA-based database processor for fast database analytics

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

High-performance DCT architecture based on angle recoding CORDIC and Scale-Free Factor

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2016, 2016 IEEE Sixth International Conference on Communications and Electronics (ICCE).

Quick Boot of Trusted Execution Environment With Hardware Accelerators

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2020, IEEE Access.

Frequent items counter based on binary decoders

Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham, 2018, IEICE Electron. Express.

A hybrid adaptive CORDIC in 65nm SOTB CMOS process

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations

Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, 2018, 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

A proposed adaptive image segmentation method based on Local Excitatory Global Inhibitory region growing

Trong-Thuc Hoang, Trong-Tu Bui, Quang-Trung Tran, 2014, 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE).

A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip

Trong-Thuc Hoang, Cong-Kha Pham, Quynh Nguyen Quang Nhu, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3

Trong-Thuc Hoang, Cong-Kha Pham, Kuniyasu Suzaki, 2021, 2021 18th International SoC Design Conference (ISOCC).

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse

Trong-Thuc Hoang, Cong-Kha Pham, Kuniyasu Suzaki, 2021, IEEE Access.

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction

Trong-Thuc Hoang, Cong-Kha Pham, Xuan-Tu Tran, 2021, IEICE Electronics Express.

A proposal for enhancing training speed in deep learning models based on memory activity survey

Trong-Thuc Hoang, Cong-Kha Pham, Xuan-Tu Tran, 2021, IEICE Electron. Express.

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC with Random Dynamic Frequency Scaling Countermeasure

Trong-Thuc Hoang, Cong-Kha Pham, Kuniyasu Suzaki, 2021, IEEE Access.

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Trong-Thuc Hoang, Cong-Kha Pham, Kuniyasu Suzaki, 2021, IEEE Access.

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture

Trong-Thuc Hoang, Cong-Kha Pham, Kuniyasu Suzaki, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications

Trong-Thuc Hoang, Cong-Kha Pham, Koichiro Ishibashi, 2021, 2021 18th International SoC Design Conference (ISOCC).