Po-Chang Tsai

Test Data Compression for Minimum Test Application Time

Ching-Hung Lin, Sying-Jyan Wang, Po-Chang Tsai, 2007, J. Inf. Sci. Eng..

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture

Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, 2007, 16th Asian Test Symposium (ATS 2007).

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

Sying-Jyan Wang, Po-Chang Tsai, Sying-Jyan Wang, 2006, 2006 15th Asian Test Symposium.

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

Sying-Jyan Wang, Po-Chang Tsai, 2006 .

FSM-based programmable memory BIST with macro command

Sying-Jyan Wang, Po-Chang Tsai, Feng-Ming Chang, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).