Jorge Pernillo

A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS

Jorge Pernillo, Michael P. Flynn, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 9b 1GS/s 27mW two-stage pipeline ADC in 45nm SOI-CMOS

Jorge Pernillo, Michael P. Flynn, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

End of the CMOS Scaling Roadmap ADCs

Jorge Pernillo, Michael P. Flynn, 2007 .

A 9b 2GS/s 45mW 2X-interleaved ADC

Jorge Pernillo, Michael P. Flynn, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

Jorge Pernillo, Mohammad Ranjbar, Sudeep Bhoja, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC

Jorge Pernillo, Michael P. Flynn, Lu Jie, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS

Jorge Pernillo, K. Gopalakrishnan, Jamal Riani, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

ISSCC 2016 / SESSION 3 / ULTRA HIGH-SPEED TRANSCEIVERS / 3 . 4 3 . 4 A 40 / 50 / 100 Gb / s PAM-4 Ethernet Transceiver in 28 nm CMOS

Jorge Pernillo, Sudeep Bhoja, Jamal Riani, 2015 .