Kyoji Yamashita

发表

Development of next-generation mask inspection method by using the feature of mask image captured with 199-nm inspection optics

Yoshitake Tsuji, Nobutaka Kikuiri, Shingo Murakami, 2006, SPIE Photomask Technology.

High-performance DUV inspection system for 100-nm generation masks

Ikunao Isomura, Kyoji Yamashita, Hideo Tsuchiya, 2002, Photomask Japan.

A Design Hierarchy of IC Interconnects and Gate Patterns

Akio Misaka, Kyoji Yamashita, Shinji Odanaka, 1999 .

Automatic photomask defect classification method

Kyoji Yamashita, Kazuto Matsuki, Kiminobu Akeno, 1996, Photomask and Next Generation Lithography Mask Technology.

New die-to-database mask inspection system with i-line optics for 256-Mb and 1-Gb DRAMs

Kyoji Yamashita, Hideo Tsuchiya, Toru Tojo, 1997, Photomask and Next Generation Lithography Mask Technology.

Gray map reference pattern generator of a die-to-database mask inspection system for 256-Mb and 1-Gb DRAMs

Ikunao Isomura, Kyoji Yamashita, Hideo Tsuchiya, 1998, Photomask and Next Generation Lithography Mask Technology.

A test structure for two-dimensional analysis of MOSFETs by hot-carrier-induced photoemission

Kyoji Yamashita, Hiroaki Takeuchi, Akira Muramatsu, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

Variable sensitivity detection (VSD) technology for screening SRAF nuisance defects

Yoshitake Tsuji, Ikunao Isomura, Yukio Tamura, 2009, Photomask Japan.

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2005, IEICE Trans. Electron..

A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation

Kyoji Yamashita, Takashi Ohzone, Toshihiro Matsuda, 2003, International Conference on Microelectronic Test Structures, 2003..

Correlation method of circuit-performance and technology fluctuations for improved design reliability

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2001, ASP-DAC '01.

Circuit-Simulation Model of C_ Changes in Small-Size MOSFETs Due to High Channel-Field Gradients( the IEEE International Conference on SISPAD '02)

Kyoji Yamashita, Shigetaka Kumashiro, T. Yamaguchi, 2003 .

15.1 A Novel Local Interconnect Technology for High-Performance Logic LSIs with Embe M

Kyoji Yamashita, A. Kanda, M. Ogura, 1996 .

Design for nanoimprint lithography: hot spot modification through total NIL process simulation

Kyoji Yamashita, Takuya Kono, Tetsuro Nakasugi, 2018, Advanced Lithography.

Half-tone PSM inspection sensitivity of 257-nm light source MC-3000

Kyoji Yamashita, Hideo Tsuchiya, Takeshi Fujiwara, 2002, SPIE Photomask Technology.

RLT uniformity improvement utilizing multi-scale NIL process simulation

Kyoji Yamashita, Ryoichi Inanami, Shimon Maeda, 2017, Advanced Lithography.

Detecting CD error or transmission error of photomask patterns

Kyoji Yamashita, 1998, Photomask Technology.

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2003, ASP-DAC '03.

An electrothermal circuit simulation using an equivalent thermal network for electrostatic discharge (ESD)

Kyoji Yamashita, Atsushi Hori, Shinji Odanaka, 1994, Proceedings of 1994 VLSI Technology Symposium.

Mask defect inspection method by database comparison with 0.25-0.35 μm sensitivity

Akira Ono, Kyoji Yamashita, Hideo Tsuchiya, 1994 .

Inspection apparatus for defect of pattern

Kyoji Yamashita, 山下恭司, 1992 .

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2005, IEICE Trans. Electron..

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Kyoji Yamashita, Masayuki Hatano, Sachiko Kobayashi, 2016, SPIE Advanced Lithography.

A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing

Kyoji Yamashita, Atsushi Hori, Shinji Odanaka, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

Kyoji Yamashita, Shinji Odanaka, Hiroyuki Umimoto, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.