Anton Tsertov

发表

Automated software-based self-test generation for microprocessors

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

Raimund Ubar, Jaan Raik, Artjom Jasnetski, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On in-system programming of non-volatile memories

Sergei Devadze, Artur Jutman, Artjom Jasnetski, 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

Automated software-based in-field self-test program synthesis

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2017 .

SoC and Board Modeling for Processor-Centric Board Testing

Raimund Ubar, Artur Jutman, Anton Tsertov, 2011, 2011 14th Euromicro Conference on Digital System Design.

In-system programming of non-volatile memories on microprocessor-centric boards

Sergei Devadze, Artur Jutman, Artjom Jasnetski, 2014 .

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models

Raimund Ubar, Sergei Devadze, Artur Jutman, 2011, 2011 Asian Test Symposium.

VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

Ian O'Connor, Jaan Raik, Sergei Kostin, 2016, IFIP Advances in Information and Communication Technology.

Software-Based Self-Test for Microprocessors with High-Level Decision Diagrams. Mikroprotsessorite tarkvara-põhine enesetestimine kõrgtasandi otsustusdiagrammide põhjal

Anton Tsertov, Raimund-Johannes Ubar, 2018 .

High-level modeling and testing of multiple control faults in digital systems

Raimund Ubar, Mario Schölzel, Artjom Jasnetski, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Giovanni Squillero, Artur Jutman, Anton Tsertov, 2019, 2019 IEEE European Test Symposium (ETS).

Laboratory framework TEAM for investigating the dependability issues of microprocessor systems

Raimund Ubar, Helena Kruus, Artjom Jasnetski, 2014, 10th European Workshop on Microelectronics Education (EWME).

Software-based self-test generation for microprocessors with high-level decision diagrams

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2014, Latin American Test Workshop - LATW.

Testing beyond the SoCs in a lego style

Sergei Devadze, Artur Jutman, Anton Tsertov, 2010, 2010 East-West Design & Test Symposium (EWDTS).

IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring

Sergei Devadze, Artur Jutman, Anton Tsertov, 2018, 2018 IEEE AUTOTESTCON.

Towards a Suite of IEEE 1687 Benchmark Networks

Farrokh Ghani Zadegan, Artur Jutman, Riccardo Cantoro, 2016 .

FPGA-controlled PCBA power-on self-test using processor's debug features

Matteo Sonza Reorda, Ernesto Sánchez, Julio Pérez Acle, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

High-level test data generation for software-based self-test in microprocessors

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2017, 2017 6th Mediterranean Conference on Embedded Computing (MECO).

On automatic software-based self-test program generation based on high-level decision diagrams

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2016, 2016 17th Latin-American Test Symposium (LATS).

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL

Giovanni Squillero, Artur Jutman, Anton Tsertov, 2019, 2019 IEEE International Test Conference (ITC).

A suite of IEEE 1687 benchmark networks

Matteo Sonza Reorda, Farrokh Ghani Zadegan, Artur Jutman, 2016, 2016 IEEE International Test Conference (ITC).

Software-based self-test generation for microprocessors with high-level decision diagrams

Raimund Ubar, Artjom Jasnetski, Anton Tsertov, 2014, 2014 15th Latin American Test Workshop - LATW.