Yasumoto Tomita

发表

Acceleration of Structural Analysis Simulations using CNN-based Auto-Tuning of Solver Tolerance

Takuji Yamamoto, Amir Haderbache, Koichi Shirahata, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2010 .

An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

Hideo Yamashita, Hiroshi Okano, Yasumoto Tomita, 2017, 2017 Symposium on VLSI Circuits.

A 24-Gb/s source-series terminated driver with inductor peaking in 28-nm CMOS

Takuji Yamamoto, Hirotaka Tamura, Yasumoto Tomita, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

Takushi Hashida, Yoichi Koyanagi, Hirotaka Tamura, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

Hideo Yamashita, Hiroshi Okano, Yasumoto Tomita, 2017, VLSIC 2017.

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2010 .

An FPGA-accelerated partial duplicate image retrieval engine for a document search system

Yasuhiro Watanabe, Takayuki Baba, Yasumoto Tomita, 2016, 2016 IEEE Winter Conference on Applications of Computer Vision (WACV).

An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

Hideo Yamashita, Hiroshi Okano, Yasumoto Tomita, 2017, 2017 Symposium on VLSI Technology.

What is a good way to expand a silicon value to a solution value?

Zhihua Wang, Tihao Chiang, Takayuki Kawahara, 2014, A-SSCC.

An FPGA-accelerated partial image matching engine for massive media data searching systems

Yasuhiro Watanabe, Atsushi Ike, Takayuki Baba, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 0.12mm2 5Gbps receiver with a level shifting equalizer and a cumulative-histogram-based adaptation engine

Takuji Yamamoto, Hirotaka Tamura, Yasumoto Tomita, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

Hirotaka Tamura, Tadahiro Kuroda, Masaya Kibune, 2004, VLSIC 2004.

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2–;10 Gb/s ADC-based receivers

Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, 2010, IEEE Custom Integrated Circuits Conference 2010.

Speed-Up of Object Detection Neural Network with GPU

Atsushi Ike, Akira Nakagawa, Koichi Shirahata, 2018, 2018 25th IEEE International Conference on Image Processing (ICIP).

An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS

Yoichi Koyanagi, Hirotaka Tamura, Yasumoto Tomita, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A dynamic offset control technique for comparator design in scaled CMOS technology

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Memory reduction method for deep neural network training

Atsushi Ike, Koichi Shirahata, Yasumoto Tomita, 2016, 2016 IEEE 26th International Workshop on Machine Learning for Signal Processing (MLSP).

A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2009, 2009 Symposium on VLSI Circuits.

GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning

Atsushi Ike, Koichi Shirahata, Yasumoto Tomita, 2018 .

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Yoshiyasu Doi, Hirotaka Tamura, Masaya Kibune, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

Takuji Yamamoto, Hirotaka Tamura, Masaya Kibune, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Split capacitor DAC mismatch calibration in successive approximation ADC

Sanroku Tsukamoto, Hirotaka Tamura, Tadahiro Kuroda, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Yoshiyasu Doi, Takayuki Shibasaki, Takuji Yamamoto, 2010, IEEE Journal of Solid-State Circuits.

GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning

Atsushi Ike, Koichi Shirahata, Yasumoto Tomita, 2017, 2017 Fifth International Symposium on Computing and Networking (CANDAR).

An 8-to-16GHz 28nm CMOS clock distribution circuit based on mutual-injection-locked ring oscillators

Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, 2013, 2013 Symposium on VLSI Circuits.