C. Hobbs

发表

Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application

Geoffrey Yeap, W. Maszara, P. Kirsch, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Challenges of III–V materials in advanced CMOS logic

T. Ngai, G. Bersuker, R. Jammy, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetration

J. Mogab, P.G.Y. Tsui, M. Khare, 1997, International Electron Devices Meeting. IEDM Technical Digest.

32nm general purpose bulk CMOS technology for high performance applications at low voltage

S. Samavedam, M. Sherony, F. Arnaud, 2008, 2008 IEEE International Electron Devices Meeting.

Dual-metal gate CMOS with HfO2 gate dielectric

P. Abramowitz, J. Conner, E. Luckowski, 2002, Digest. International Electron Devices Meeting,.

80 nm poly-Si gate CMOS with HfO/sub 2/ gate dielectric

J. Conner, S. Bagchi, L. Prabhu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

M. Mendicino, D. Jovanovic, O. Adetutu, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Performance and variability in multi-VT FinFETs using fin doping

P. Y. Hung, T. Ngai, R. Jammy, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

P. D. Kirsch, K. Matthews, D.-H Kim, 2013, 2013 IEEE International Electron Devices Meeting.

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

T. Michalak, G. Bersuker, P. D. Kirsch, 2013, 2013 IEEE International Electron Devices Meeting.

PBTI improvement in gate last HfO2 gate dielectric nMOSFET due to Zr incorporation

G. Bersuker, R. Jammy, P. D. Kirsch, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Conformal, low-damage shallow junction technology (Xj∼5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node

R. Jammy, J. Snow, P. D. Kirsch, 2012, 2012 12th International Workshop on Junction Technology.

Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET

S. Datta, R. Jammy, P. Majhi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

G. Bersuker, P. D. Kirsch, K. Matthews, 2013, IEEE Transactions on Device and Materials Reliability.

New insights into SILC-based life time extraction

L. Larcher, T. Ngai, G. Bersuker, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Fermi level pinning at the polySi/metal oxide interface

S. Samavedam, V. Dhandapani, L. Hebert, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Impact of TiN Metal gate on NBTI assessed by interface states and fast transient effect characterization

X. Garros, G. Ghibaudo, M. Rafik, 2007, 2007 IEEE International Electron Devices Meeting.

Plasma doping of silicon fin structures

C. Hobbs, F. Torregrosa, L. Roux, 2011, 11th International Workshop on Junction Technology (IWJT).

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

R. Jammy, P. D. Kirsch, P. Majhi, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Advanced contact and junction technologies for improved parasitic resistance and short channel immunity in FinFETs beyond 22nm node

P. Y. Hung, R. Jammy, P. D. Kirsch, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement

R. Jammy, P. D. Kirsch, K. Matthews, 2012, 2012 International Electron Devices Meeting.

Reducing Rext in laser annealed enhancement-mode In0.53Ga0.47As surface channel n-MOSFET

P. Y. Hung, G. Bersuker, R. Jammy, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

A. S. Oates, G. Bersuker, P. D. Kirsch, 2014, 2014 IEEE International Reliability Physics Symposium.

Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

P. Y. Hung, F. Khaja, K. Matthews, 2014, 2014 IEEE International Electron Devices Meeting.

ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability

S. Kalpat, O. Adetutu, L. Hebert, 2003, IEEE International Electron Devices Meeting 2003.